From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 25 Feb 2022 18:31:02 +0000 (+0000)
Subject: restore naming convention "cs_r" on DFI Interface
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d038760d79f47e69cb1ca0920a858f29fcd1e09;p=gram.git

restore naming convention "cs_r" on DFI Interface
---

diff --git a/gram/core/multiplexer.py b/gram/core/multiplexer.py
index 458c301..69d9fb4 100644
--- a/gram/core/multiplexer.py
+++ b/gram/core/multiplexer.py
@@ -157,7 +157,7 @@ class _Steerer(Elaboratable):
                 return cmd.valid & cmd.ready & getattr(cmd, attr)
 
         for i, (phase, sel) in enumerate(zip(self.dfi.phases, self.sel)):
-            nranks = len(phase.cs)
+            nranks = len(phase.cs_n)
             rankbits = log2_int(nranks)
             if hasattr(phase, "reset_n"):
                 m.d.comb += phase.reset_n.eq(1)
@@ -171,15 +171,15 @@ class _Steerer(Elaboratable):
                 m.d.comb += rank_decoder.i.eq((Array(cmd.ba[-rankbits:] for cmd in self.commands)[sel]))
                 if i == 0:  # Select all ranks on refresh.
                     with m.If(sel == STEER_REFRESH):
-                        m.d.sync += phase.cs.eq(1)
+                        m.d.sync += phase.cs_n.eq(0)
                     with m.Else():
-                        m.d.sync += phase.cs.eq(rank_decoder.o)
+                        m.d.sync += phase.cs_n.eq(rank_decoder.o)
                 else:
-                    m.d.sync += phase.cs.eq(rank_decoder.o)
+                    m.d.sync += phase.cs_n.eq(rank_decoder.o)
                 m.d.sync += phase.bank.eq(Array(cmd.ba[:-rankbits] for cmd in self.commands)[sel])
             else:
                 m.d.sync += [
-                    phase.cs.eq(1),
+                    phase.cs_n.eq(0),
                     phase.bank.eq(Array(cmd.ba for cmd in self.commands)[sel]),
                 ]
 
diff --git a/gram/dfii.py b/gram/dfii.py
index f9d4de5..8b5537f 100644
--- a/gram/dfii.py
+++ b/gram/dfii.py
@@ -36,14 +36,15 @@ class PhaseInjector(Elaboratable):
 
         with m.If(self._command_issue.w_stb):
             m.d.comb += [
-                self._phase.cs.eq(Repl(value=self._command.w_data[0], count=len(self._phase.cs))),
+                self._phase.cs_n.eq(Repl(value=~self._command.w_data[0],
+                                       count=len(self._phase.cs_n))),
                 self._phase.we.eq(self._command.w_data[1]),
                 self._phase.cas.eq(self._command.w_data[2]),
                 self._phase.ras.eq(self._command.w_data[3]),
             ]
         with m.Else():
             m.d.comb += [
-                self._phase.cs.eq(Repl(value=0, count=len(self._phase.cs))),
+                self._phase.cs_n.eq(Repl(value=1, count=len(self._phase.cs_n))),
                 self._phase.we.eq(0),
                 self._phase.cas.eq(0),
                 self._phase.ras.eq(0),
diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index 91c4799..d76b764 100644
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -13,7 +13,7 @@ def phase_description(addressbits, bankbits, nranks, databits):
         ("address", addressbits, DIR_FANOUT),
         ("bank", bankbits, DIR_FANOUT),
         ("cas", 1, DIR_FANOUT),
-        ("cs", nranks, DIR_FANOUT),
+        ("cs_n", nranks, DIR_FANOUT),
         ("ras", 1, DIR_FANOUT),
         ("we", 1, DIR_FANOUT),
         ("clk_en", nranks, DIR_FANOUT),
diff --git a/gram/phy/fakephy.py b/gram/phy/fakephy.py
index 6a409c4..5feb583 100644
--- a/gram/phy/fakephy.py
+++ b/gram/phy/fakephy.py
@@ -178,13 +178,13 @@ class DFIPhaseModel(Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
-        with m.If(self.phase.cs & self.phase.ras & ~self.phase.cas):
+        with m.If(~self.phase.cs_n & self.phase.ras & ~self.phase.cas):
             m.d.comb += [
                 self.activate.eq(~self.phase.we),
                 self.precharge.eq(self.phase.we),
             ]
 
-        with m.If(self.phase.cs & ~self.phase.ras & self.phase.cas):
+        with m.If(~self.phase.cs_n  & ~self.phase.ras & self.phase.cas):
             m.d.comb += [
                 self.write.eq(self.phase.we),
                 self.read.eq(~self.phase.we),
@@ -340,7 +340,8 @@ class DFITimingsChecker(Elaboratable):
             ps = Signal().like(cnt)
             m.d.comb += ps.eq((cnt + np)*int(self.timings["tCK"]))
             state = Signal(4)
-            m.d.comb += state.eq(Cat(phase.we, phase.cas, phase.ras, phase.cs))
+            m.d.comb += state.eq(Cat(phase.we, phase.cas, phase.ras,
+                                     phase.cs_n))
             all_banks = Signal()
 
             m.d.comb += all_banks.eq(