From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 02:30:38 +0000 (+0000)
Subject: CSR decoding
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d139544972147f9cc9c0c2727c7d53a689a8ad9;p=rv32.git

CSR decoding
---

diff --git a/cpu.py b/cpu.py
index e0a6881..b79615c 100644
--- a/cpu.py
+++ b/cpu.py
@@ -610,6 +610,19 @@ class CPU(Module):
                                  csr_op_is_valid)
 
         #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
+        # CSR decoding
+        csr_number = Signal(12)
+        csr_input_value = Signal(32)
+        csr_reads = Signal()
+        csr_writes = Signal()
+
+        self.comb += csr_number.eq(dc.immediate)
+        self.comb += csr_input_value.eq(Mux(dc.funct3[2],
+                                            dc.rs1,
+                                            register_rs1))
+        self.comb += csr_reads.eq(dc.funct3[1] | (dc.rd != 0))
+        self.comb += csr_writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
+
 
 if __name__ == "__main__":
     example = CPU()