From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 4 Jan 2018 12:23:29 +0000 (+0100)
Subject: Temporarily derive blackbox modules in hierarchy to evaluate port widths
X-Git-Tag: yosys-0.8~240
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d140a44ebfff31876778a4e70102763aa1cb595;p=yosys.git

Temporarily derive blackbox modules in hierarchy to evaluate port widths

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index c460fbbfc..524d57854 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -620,6 +620,8 @@ struct HierarchyPass : public Pass {
 			}
 		}
 
+		std::set<Module*> blackbox_derivatives;
+
 		for (auto module : design->modules())
 		for (auto cell : module->cells())
 		{
@@ -628,9 +630,17 @@ struct HierarchyPass : public Pass {
 
 			Module *m = design->module(cell->type);
 
-			if (m == nullptr || m->get_bool_attribute("\\blackbox"))
+			if (m == nullptr)
 				continue;
 
+			if (m->get_bool_attribute("\\blackbox") && cell->parameters.size()) {
+				IdString new_m_name = m->derive(design, cell->parameters);
+				if (new_m_name != m->name) {
+					m = design->module(new_m_name);
+					blackbox_derivatives.insert(m);
+				}
+			}
+
 			for (auto &conn : cell->connections())
 			{
 				Wire *w = m->wire(conn.first);
@@ -673,6 +683,9 @@ struct HierarchyPass : public Pass {
 			}
 		}
 
+		for (auto module : blackbox_derivatives)
+			design->remove(module);
+
 		log_pop();
 	}
 } HierarchyPass;