From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Aug 2022 15:02:18 +0000 (+0100)
Subject: sigh, update setvl tests, to spec, and ISACaller
X-Git-Tag: sv_maxu_works-initial~80
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d1e5215b1089fa7e2f1bfba53f6d012ba6dd927;p=openpower-isa.git

sigh, update setvl tests, to spec, and ISACaller
https://libre-soc.org/openpower/sv/setvl/
see Rc=1 section: it is possible to have Rc=1, RT=0, RA!=0 which
means "set VL but do not set RT" which *still* requires that Rc=1
be updated - not from RT but from VL
---

diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn
index b19e3af6..7d60e901 100644
--- a/openpower/isa/simplev.mdwn
+++ b/openpower/isa/simplev.mdwn
@@ -29,7 +29,7 @@ Pseudo-code:
     if (vf & (¬vs) & ¬(ms)) = 1 then
         step <- SVSTATE_NEXT(SVi, 0b0)
         if _RT != 0 then
-           RT <- [0]*57 || step
+           GPR(_RT) <- [0]*57 || step
     else
         overflow <- 0b0
         VLimm <- SVi + 1
@@ -56,7 +56,7 @@ Pseudo-code:
         SVSTATE[0:6] <- MVL
         SVSTATE[7:13] <- VL
         if _RT != 0 then
-           RT <- [0]*57 || VL
+           GPR(_RT) <- [0]*57 || VL
         if ((¬vs) & ¬(ms)) = 0 then
             # set requested Vertical-First mode, clear persist
             SVSTATE[63] <- vf
diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index bb928aba..58d2dc3f 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1440,7 +1440,12 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                 rc_en = yield self.dec2.e.do.rc.rc
         if rc_en and ins_name not in ['svstep']:
             regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
-            self.handle_comparison(results, regnum, overflow)
+            cmps = results
+            # hang on... for `setvl` actually you want to test SVSTATE.VL
+            if ins_name == 'setvl':
+                vl = results[0].vl
+                cmps = (SelectableInt(vl, 64), overflow,)
+            self.handle_comparison(cmps, regnum, overflow)
 
         # any modified return results?
         if info.write_regs:
diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index 3b2097cf..c6ddffcd 100644
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -220,6 +220,48 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(CR0[CRFields.GT], 1)
             self.assertEqual(CR0[CRFields.SO], 0)
 
+    def test_5_setvl_rt0_rc1(self):
+        """odd one. Rc=1, RT=0, RA!=0, so RT does not get set, but VL does.
+        confirms that when Rc=1 and RT is unmodified that CR0 still is updated
+        """
+        lst = SVP64Asm(["setvl. 0, 4, 5, 0, 1, 1",
+                        ])
+        lst = list(lst)
+
+        # SVSTATE (in this case, MAXVL=5) which is going to get erased by setvl
+        # r4 (RA) is 4. and Rc=1. therefore, CR0 should be set to GT
+        svstate = SVP64State()
+        svstate.maxvl = 5 # MAXVL
+        print ("SVSTATE", bin(svstate.asint()))
+
+        initial_regs = [0] * 32
+        initial_regs[4] = 127 # overlimit, should set CR0.SO=1, and CR0.GT=1
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, svstate=svstate,
+                                       initial_regs=initial_regs)
+            print ("SVSTATE after", bin(sim.svstate.asint()))
+            print ("        vl", bin(sim.svstate.vl))
+            print ("        mvl", bin(sim.svstate.maxvl))
+            print ("    srcstep", bin(sim.svstate.srcstep))
+            print ("    dststep", bin(sim.svstate.dststep))
+            print ("     vfirst", bin(sim.svstate.vfirst))
+            self.assertEqual(sim.svstate.vl, 5)
+            self.assertEqual(sim.svstate.maxvl, 5)
+            self.assertEqual(sim.svstate.srcstep, 0)
+            self.assertEqual(sim.svstate.dststep, 0)
+            self.assertEqual(sim.svstate.vfirst, 0)
+            print("      gpr0", sim.gpr(0))
+            self.assertEqual(sim.gpr(0), SelectableInt(0, 64)) # unmodified
+            print("      gpr4", sim.gpr(4))
+            self.assertEqual(sim.gpr(4), SelectableInt(127, 64)) # unmodified
+            CR0 = sim.crl[0]
+            print("      CR0", bin(CR0.get_range().value))
+            self.assertEqual(CR0[CRFields.EQ], 0)
+            self.assertEqual(CR0[CRFields.LT], 0)
+            self.assertEqual(CR0[CRFields.GT], 1)
+            self.assertEqual(CR0[CRFields.SO], 1)
+
     def test_svstep_1(self):
         lst = SVP64Asm(["setvl 0, 0, 10, 1, 1, 1", # actual setvl (VF mode)
                         "setvl 0, 0, 1, 1, 0, 0", # svstep