From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Oct 2018 23:56:34 +0000 (+0100)
Subject: split out sv_reg_t elwidth into separate base class
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d29d6553268ffcfa02b64dec02cc3716b6b54ac;p=riscv-isa-sim.git

split out sv_reg_t elwidth into separate base class
---

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index a5ba035..6dbf7e0 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -104,7 +104,7 @@ sv_reg_t sv_proc_t::get_intreg(reg_t reg)
 {
     uint8_t elwidth = _insn->reg_elwidth(reg, true);
     uint64_t data = _insn->p->get_state()->XPR[reg];
-    return sv_reg_t(data /*, elwidth*/);
+    return sv_reg_t(data , elwidth);
 }
 
 #define GET_REG(name) \
diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 4e9689e..6375a1a 100644
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -3,34 +3,61 @@
 
 class sv_sreg_t;
 
-class sv_reg_t {
+class sv_regbase_t {
 public:
-    sv_reg_t(uint64_t _reg) : reg(_reg) , elwidth(0) { } // default elwidth
-    sv_reg_t(uint64_t _reg, uint8_t _elwidth) : reg(_reg), elwidth(_elwidth) {}
+    sv_regbase_t() : elwidth(0) { } // default elwidth
+    sv_regbase_t(uint8_t _elwidth) : elwidth(_elwidth) {}
 
-    uint64_t reg;
     uint8_t elwidth;
 public:
-  uint64_t get_data() { return reg; }
-  uint8_t get_width() { return elwidth; }
+  uint8_t get_width() const { return elwidth; }
+  uint8_t get_width(sv_regbase_t const&r) {
+    // bitfield 0b00=default, 0b01=default/2, 0b10=default*2, 0b11=8-bit
+    uint8_t tb[16] = { 0x0, // default-default: default
+                       0x0, // default-default/2: default
+                       0x2, // default-default*2: default*2
+                       0x0, // default-8: default
+                       0x0, // default/2-default: default
+                       0x1, // default/2-default/2: default/2
+                       0x2, // default/2-default*2: default*2
+                       0x1, // default/2-8: default*2
+                       0x2, // default*2-default: default*2
+                       0x2, // default*2-default/2: default*2
+                       0x2, // default*2-default*2: default*2
+                       0x2, // default*2-8: default*2
+                       0x0, // 8-default: default
+                       0x1, // 8-default/2: default/2
+                       0x2, // 8-default*2: default*2
+                       0x3  // 8-8: 8
+    };
+    return tb[elwidth|(r.elwidth<<2)];
+    }
+};
+
+class sv_reg_t : sv_regbase_t {
+public:
+    sv_reg_t(uint64_t _reg) : sv_regbase_t(), reg(_reg) { } // default elwidth
+    sv_reg_t(uint64_t _reg, uint8_t _elwidth) : sv_regbase_t(_elwidth), reg(_reg)
+                                                {}
 
-  operator uint64_t() const & { return reg; }
-  operator sv_sreg_t() const &;
+    uint64_t reg;
+public:
+
+  operator uint64_t() const& { return reg; }
+  operator sv_sreg_t() const&;
 };
 
-class sv_sreg_t {
+class sv_sreg_t : sv_regbase_t {
 public:
-    sv_sreg_t(int64_t _reg) : reg(_reg) , elwidth(0) {} // default elwidth
-    sv_sreg_t(int64_t _reg, uint8_t _elwidth) : reg(_reg), elwidth(_elwidth) {}
+    sv_sreg_t(int64_t _reg) : sv_regbase_t(), reg(_reg) {} // default elwidth
+    sv_sreg_t(int64_t _reg, uint8_t _elwidth) : sv_regbase_t(_elwidth),
+                                                reg(_reg) {}
 
     int64_t reg;
-    uint8_t elwidth;
 public:
-  int64_t get_data() { return reg; }
-  uint8_t get_width() { return elwidth; }
 
   operator int64_t() const& { return reg; }
-  operator sv_reg_t() const& { return sv_reg_t((uint64_t)reg, elwidth); }
+  operator sv_reg_t() const& { return sv_reg_t((uint64_t)reg, get_width()); }
 };
 
 inline sv_reg_t::operator sv_sreg_t() const &