From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Sun, 24 Jan 2021 17:01:24 +0000 (+0000)
Subject: arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare
X-Git-Tag: develop-gem5-snapshot~231
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d2f227e1d95e428a51b230611ed42e02a7f8fe1;p=gem5.git

arch-arm: Add set_reg_idx_arr to SveStructMemSIMicroopDeclare

This should have been part of:

https://gem5-review.googlesource.com/c/public/gem5/+/38381

Change-Id: I1914fdcd0382fc95dcead2eafa09de12a43776ab
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39635
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index 8bfb423e3..f635870b0 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -911,6 +911,7 @@ def template SveStructMemSIMicroopDeclare {{
             numRegs(_numRegs), regIndex(_regIndex),
             memAccessFlags(ArmISA::TLB::AllowUnaligned)
         {
+            %(set_reg_idx_arr)s;
             %(constructor)s;
             baseIsSP = isSP(_base);
         }