From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 21 Dec 2021 16:32:55 +0000 (+0000)
Subject: enable I-Cache wishbone memory type in issuer_verilog.py if MMU requested
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d386cfefd991ca19d6b59b08e09a56c2e82886f;p=soc.git

enable I-Cache wishbone memory type in issuer_verilog.py if MMU requested
---

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index b3b7410d..ad9b7e8d 100644
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -77,9 +77,10 @@ if __name__ == '__main__':
     # decide which memory type to configure
     if args.mmu:
         ldst_ifacetype = 'mmu_cache_wb'
+        imem_ifacetype = 'mmu_cache_wb'
     else:
         ldst_ifacetype = 'bare_wb'
-    imem_ifacetype = 'bare_wb'
+        imem_ifacetype = 'bare_wb'
 
     pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
                          imem_ifacetype=imem_ifacetype,