From: lkcl <lkcl@web>
Date: Fri, 26 Jul 2019 21:50:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~4300
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d419489a87ce9eebac17208910b67be6a2f0db9;p=libreriscv.git

---

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 53dda30b8..f5a607ab5 100644
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -91,7 +91,7 @@ where 1 <= MVL <= XLEN
 
 ## SUBVL - Sub Vector Length
 
-This is a "group by quantity" that effectivrly asks each iteration
+This is a "group by quantity" that effectively asks each iteration
 of the hardware loop to load SUBVL elements of width elwidth at a
 time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
 operation issued, SUBVL operations are issued.