From: Marcin Kościelnicki <koriakin@0x04.net>
Date: Tue, 13 Aug 2019 19:47:27 +0000 (+0200)
Subject: README updates
X-Git-Tag: working-ls180~1097^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d5d82e2b6f7d369c0d41b499646a8719ff0bc20;p=yosys.git

README updates
---

diff --git a/README.md b/README.md
index d9989eb29..767a0fb61 100644
--- a/README.md
+++ b/README.md
@@ -329,6 +329,20 @@ Verilog Attributes and non-standard features
   that represent module parameters or localparams (when the HDL front-end
   is run in -pwires mode).
 
+- The ``clkbuf_inhibit`` attribute can be set on a wire to prevent
+  automatic clock buffer insertion by ``clkbufmap``.
+
+- The ``clkbuf_sink`` attribute can be set on an input port of a blackbox
+  module to request clock buffer insertion by the ``clkbufmap`` pass.
+
+- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
+  module to mark it as a clock buffer output, and thus prevent ``clkbufmap``
+  from inserting another clock buffer on a net driven by such output.
+
+- The ``iopad_external_pin`` attribute on a blacbox module's port marks
+  it as the external-facing pin of an I/O pad, and prevents ``iopadmap``
+  from inserting another pad cell on it.
+
 - In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset