From: lkcl <lkcl@web>
Date: Tue, 14 Sep 2021 14:39:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~141
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d66fd65e00decf4cebad6bfb91e0cf283f98f05;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 48fc1a415..1e149f901 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -60,15 +60,14 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
 
 | 4 | 5 | 19-20 |  21 | 22   23 |  description     |
 | - | - | ----- | --- |---------|----------------- |
-| / | / | 00    |   0 |  dz  sz | normal mode                      |
+|sz |SNZ| 00    |   0 |  dz  /  | normal mode                      |
 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
-|dz |VLi| 01    | inv |  CR-bit | Ffirst 3-bit mode      |
-|sz |VLi| 01    | inv |  dz Rc1 | Ffirst 5-bit mode       |
-| / | / | 10    |   / | /   /   |  RESERVED |
+|dz |SNZ| VLI 1 | inv |  CR-bit | Ffirst 3-bit mode      |
+|sz |SNZ| VLI 1 | inv |  dz Rc1 | Ffirst 5-bit mode       |
 |sz |SNZ| 11    | inv | CR-bit  |  3-bit pred-result CR sel |
-| / |SNZ| 11    | inv | dz  sz  |  5-bit pred-result z/nonz |
+|sz |SNZ| 11    | inv | dz  /   |  5-bit pred-result z/nonz |
 
 Fields: