From: lkcl <lkcl@web>
Date: Tue, 14 Sep 2021 14:42:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~140
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d73a44273841ce87b1eed9e59bf11187d15bee9;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 1e149f901..12af53ee7 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -64,11 +64,14 @@ SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
 | / | / | 00    |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
 | / | / | 00    |   1 | 1  CRM  | parallel reduce mode (mapreduce), SUBVL=1 |
 | / | / | 00    |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
-|dz |SNZ| VLI 1 | inv |  CR-bit | Ffirst 3-bit mode      |
-|sz |SNZ| VLI 1 | inv |  dz Rc1 | Ffirst 5-bit mode       |
+|dz |SNZ| 01/10 | inv |  CR-bit | Ffirst 3-bit mode      |
+|sz |SNZ| 01/10 | inv |  dz Rc1 | Ffirst 5-bit mode       |
 |sz |SNZ| 11    | inv | CR-bit  |  3-bit pred-result CR sel |
 |sz |SNZ| 11    | inv | dz  /   |  5-bit pred-result z/nonz |
 
+`VLI=0` when bits 19-20=0b01. 
+`VLI=1` when bits 19-20=0b10. 
+
 Fields:
 
 TODO