From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 3 Jul 2020 03:12:34 +0000 (+0100)
Subject: set only div/rem supported
X-Git-Tag: div_pipeline~164
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d785b67ed5d6de82ce956f10e31c87eabd97dc0;p=soc.git

set only div/rem supported
---

diff --git a/src/soc/fu/div/pipe_data.py b/src/soc/fu/div/pipe_data.py
index ac3e434a..3a7f35d2 100644
--- a/src/soc/fu/div/pipe_data.py
+++ b/src/soc/fu/div/pipe_data.py
@@ -3,7 +3,7 @@ from soc.fu.pipe_data import IntegerData
 from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
 from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 from ieee754.div_rem_sqrt_rsqrt.core import (
-    DivPipeCoreConfig, DivPipeCoreInputData,
+    DivPipeCoreConfig, DivPipeCoreInputData, DP,
     DivPipeCoreInterstageData, DivPipeCoreOutputData)
 
 
@@ -24,6 +24,7 @@ class DIVPipeSpec(CommonPipeSpec):
         bit_width=64,
         fract_width=64,
         log2_radix=1,
+        supported=[DP.UDivRem]
     )