From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 14 Jun 2019 20:07:56 +0000 (-0700)
Subject: Get rid of compiler warnings
X-Git-Tag: working-ls180~1237^2~105
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d85725604271c658382e8fdd8ff28275fb94b03;p=yosys.git

Get rid of compiler warnings
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 7cb311736..3f7edc627 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -190,7 +190,7 @@ struct XAigerWriter
 
 		bool abc_box_seen = false;
 
-		for (auto cell : module->cells()) {
+		for (auto cell : module->selected_cells()) {
 			if (cell->type == "$_NOT_")
 			{
 				SigBit A = sigmap(cell->getPort("\\A").as_bit());
@@ -312,7 +312,7 @@ struct XAigerWriter
 			TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
 			dict<SigBit, pool<IdString>> bit_drivers, bit_users;
 
-			for (auto cell : module->cells()) {
+			for (auto cell : module->selected_cells()) {
 				RTLIL::Module* inst_module = module->design->module(cell->type);
 				if (!inst_module || !inst_module->attributes.count("\\abc_box_id"))
 					continue;
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index fe199f886..f7f2e862a 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -243,8 +243,8 @@ struct abc_output_filter
 
 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
 		bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
-		bool keepff, std::string delay_target, std::string lutin_shared, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file,
+		bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
+		bool show_tempdir, std::string box_file, std::string lut_file,
 		std::string wire_delay)
 {
 	module = current_module;
@@ -835,7 +835,7 @@ struct Abc9Pass : public Pass {
 		std::string script_file, clk_str, box_file, lut_file;
 		std::string delay_target, lutin_shared = "-S 1", wire_delay;
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
-		bool show_tempdir = false, sop_mode = false;
+		bool show_tempdir = false;
 		vector<int> lut_costs;
 		markgroups = false;
 
@@ -997,7 +997,7 @@ struct Abc9Pass : public Pass {
 
 			if (!dff_mode || !clk_str.empty()) {
 				abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
-						delay_target, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode,
+						delay_target, lutin_shared, fast_mode, show_tempdir,
 						box_file, lut_file, wire_delay);
 				continue;
 			}
@@ -1143,7 +1143,7 @@ struct Abc9Pass : public Pass {
 				en_polarity = std::get<2>(it.first);
 				en_sig = assign_map(std::get<3>(it.first));
 				abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
-						keepff, delay_target, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode,
+						keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
 						box_file, lut_file, wire_delay);
 				assign_map.set(mod);
 			}