From: Claire Xenia Wolf <claire@clairexen.net>
Date: Wed, 9 Jun 2021 10:42:52 +0000 (+0200)
Subject: Intersynth URL
X-Git-Tag: yosys-0.10~145^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d95a7da9cd2e8cf1854215241c5df7d67ca0c1e;p=yosys.git

Intersynth URL

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---

diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 758a8792b..59173c4a2 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -68,7 +68,7 @@ struct IntersynthBackend : public Backend {
 		log("        only write selected modules. modules must be selected entirely or\n");
 		log("        not at all.\n");
 		log("\n");
-		log("http://www.clifford.at/intersynth/\n");
+		log("http://bygone.clairexen.net/intersynth/\n");
 		log("\n");
 	}
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index a3264b4cd..960078cc7 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -6999,7 +6999,7 @@ a tool for Coarse-Grain Example-Driven Interconnect Synthesis.
         only write selected modules. modules must be selected entirely or
         not at all.
 
-http://www.clifford.at/intersynth/
+http://bygone.clairexen.net/intersynth/
 \end{lstlisting}
 
 \section{write\_json -- write design to a JSON file}