From: Paul Mackerras Date: Fri, 8 Jul 2022 06:37:12 +0000 (+1000) Subject: decode1: Remove stash buffer X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2da08bcf2e64e5f77ce8b4098ae27101dceef6cc;p=microwatt.git decode1: Remove stash buffer Now that the timing of the busy signal from decode2 doesn't depend on register numbers or downstream instruction completion, we no longer need the stash buffer on the output of decode1. Signed-off-by: Paul Mackerras --- diff --git a/decode1.vhdl b/decode1.vhdl index b807054..5bc023b 100644 --- a/decode1.vhdl +++ b/decode1.vhdl @@ -30,7 +30,6 @@ end entity decode1; architecture behaviour of decode1 is signal r, rin : Decode1ToDecode2Type; - signal s : Decode1ToDecode2Type; signal f, fin : Decode1ToFetch1Type; constant illegal_inst : decode_rom_t := @@ -46,7 +45,6 @@ architecture behaviour of decode1 is (override => '0', override_decode => illegal_inst, override_unit => '0', force_single => '0'); signal ri, ri_in : reg_internal_t; - signal si : reg_internal_t; type br_predictor_t is record br_nia : std_ulogic_vector(61 downto 0); @@ -555,26 +553,12 @@ begin if rising_edge(clk) then if rst = '1' then r <= Decode1ToDecode2Init; - s <= Decode1ToDecode2Init; ri <= reg_internal_t_init; - si <= reg_internal_t_init; elsif flush_in = '1' then r.valid <= '0'; - s.valid <= '0'; - elsif s.valid = '1' then - if stall_in = '0' then - r <= s; - ri <= si; - s.valid <= '0'; - end if; - else - s <= rin; - si <= ri_in; - s.valid <= rin.valid and r.valid and stall_in; - if r.valid = '0' or stall_in = '0' then - r <= rin; - ri <= ri_in; - end if; + elsif stall_in = '0' then + r <= rin; + ri <= ri_in; end if; if rst = '1' then br.br_nia <= (others => '0'); @@ -585,7 +569,7 @@ begin end if; end if; end process; - busy_out <= s.valid; + busy_out <= stall_in; decode1_1: process(all) variable v : Decode1ToDecode2Type;