From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 27 Jun 2019 21:32:23 +0000 (+0200)
Subject: soc_sdram: allow main_ram_size > 256MB (limitation no longer exists)
X-Git-Tag: 24jan2021_ls180~1137
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2da59b29e2e2fa4884d3e295e88062b37117747f;p=litex.git

soc_sdram: allow main_ram_size > 256MB (limitation no longer exists)
---

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 144a93b6..3e95c0c7 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -66,11 +66,9 @@ class SoCSDRAM(SoCCore):
         self.submodules.sdram = ControllerInjector(
             phy, geom_settings, timing_settings, **kwargs)
 
-        # TODO: modify mem_map to allow larger memories.
         main_ram_size = 2**(geom_settings.bankbits +
                             geom_settings.rowbits +
                             geom_settings.colbits)*phy.settings.databits//8
-        main_ram_size = min(main_ram_size, 256*1024*1024)
         self.add_constant("L2_SIZE", self.l2_size)
 
         # add a Wishbone interface to the DRAM