From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Tue, 5 Dec 2017 12:51:46 +0000 (+0100)
Subject: radv/winsys: rework radv_amdgpu_bo_va_op()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2dab5e96ec54af87f651c917bffa08e6b0770eb5;p=mesa.git

radv/winsys: rework radv_amdgpu_bo_va_op()

Needed for the following commit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
index 4b11823b0a8..7cefdc8173e 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
@@ -40,19 +40,24 @@
 static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo *_bo);
 
 static int
-radv_amdgpu_bo_va_op(amdgpu_device_handle dev,
+radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys *ws,
 		     amdgpu_bo_handle bo,
 		     uint64_t offset,
 		     uint64_t size,
 		     uint64_t addr,
-		     uint64_t flags,
+		     uint32_t bo_flags,
 		     uint32_t ops)
 {
+	uint64_t flags = AMDGPU_VM_PAGE_READABLE |
+			 AMDGPU_VM_PAGE_WRITEABLE |
+			 AMDGPU_VM_PAGE_EXECUTABLE;
+
+	if ((bo_flags & RADEON_FLAG_VA_UNCACHED) && ws->info.chip_class >= GFX9)
+		flags |= AMDGPU_VM_MTYPE_UC;
+
 	size = ALIGN(size, getpagesize());
-	flags |= (AMDGPU_VM_PAGE_READABLE |
-		  AMDGPU_VM_PAGE_WRITEABLE |
-		  AMDGPU_VM_PAGE_EXECUTABLE);
-	return amdgpu_bo_va_op_raw(dev, bo, offset, size, addr,
+
+	return amdgpu_bo_va_op_raw(ws->dev, bo, offset, size, addr,
 				   flags, ops);
 }
 
@@ -66,8 +71,9 @@ radv_amdgpu_winsys_virtual_map(struct radv_amdgpu_winsys_bo *bo,
 		return; /* TODO: PRT mapping */
 
 	p_atomic_inc(&range->bo->ref_count);
-	int r = radv_amdgpu_bo_va_op(bo->ws->dev, range->bo->bo, range->bo_offset, range->size,
-				     range->offset + bo->base.va, 0, AMDGPU_VA_OP_MAP);
+	int r = radv_amdgpu_bo_va_op(bo->ws, range->bo->bo, range->bo_offset,
+				     range->size, range->offset + bo->base.va,
+				     0, AMDGPU_VA_OP_MAP);
 	if (r)
 		abort();
 }
@@ -81,8 +87,9 @@ radv_amdgpu_winsys_virtual_unmap(struct radv_amdgpu_winsys_bo *bo,
 	if (!range->bo)
 		return; /* TODO: PRT mapping */
 
-	int r = radv_amdgpu_bo_va_op(bo->ws->dev, range->bo->bo, range->bo_offset, range->size,
-				     range->offset + bo->base.va, 0, AMDGPU_VA_OP_UNMAP);
+	int r = radv_amdgpu_bo_va_op(bo->ws, range->bo->bo, range->bo_offset,
+				     range->size, range->offset + bo->base.va,
+				     0, AMDGPU_VA_OP_UNMAP);
 	if (r)
 		abort();
 	radv_amdgpu_winsys_bo_destroy((struct radeon_winsys_bo *)range->bo);
@@ -255,7 +262,8 @@ static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys_bo *_bo)
 			bo->ws->num_buffers--;
 			pthread_mutex_unlock(&bo->ws->global_bo_list_lock);
 		}
-		radv_amdgpu_bo_va_op(bo->ws->dev, bo->bo, 0, bo->size, bo->base.va, 0, AMDGPU_VA_OP_UNMAP);
+		radv_amdgpu_bo_va_op(bo->ws, bo->bo, 0, bo->size, bo->base.va,
+				     0, AMDGPU_VA_OP_UNMAP);
 		amdgpu_bo_free(bo->bo);
 	}
 	amdgpu_va_range_free(bo->va_handle);
@@ -352,11 +360,8 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
 		goto error_bo_alloc;
 	}
 
-
-	uint32_t va_flags = 0;
-	if ((flags & RADEON_FLAG_VA_UNCACHED) && ws->info.chip_class >= GFX9)
-		va_flags |= AMDGPU_VM_MTYPE_UC;
-	r = radv_amdgpu_bo_va_op(ws->dev, buf_handle, 0, size, va, va_flags, AMDGPU_VA_OP_MAP);
+	r = radv_amdgpu_bo_va_op(ws, buf_handle, 0, size, va, flags,
+				 AMDGPU_VA_OP_MAP);
 	if (r)
 		goto error_va_map;
 
@@ -426,7 +431,8 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws,
 	if (r)
 		goto error_query;
 
-	r = radv_amdgpu_bo_va_op(ws->dev, result.buf_handle, 0, result.alloc_size, va, 0, AMDGPU_VA_OP_MAP);
+	r = radv_amdgpu_bo_va_op(ws, result.buf_handle, 0, result.alloc_size,
+				 va, 0, AMDGPU_VA_OP_MAP);
 	if (r)
 		goto error_va_map;