From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Aug 2018 11:28:23 +0000 (+0200)
Subject: soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado... 
X-Git-Tag: 24jan2021_ls180~1639
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2db5424ae62c8e36e4defe5643e039c641b9a69a;p=litex.git

soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >)
---

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index a1f2a63e..80322bb5 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -75,16 +75,8 @@ class SoCSDRAM(SoCCore):
 
         if self.l2_size:
             port = self.sdram.crossbar.get_port()
-            l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width))
-            # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
-            # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
-            # Remove this workaround when fixed by Xilinx.
-            from litex.build.xilinx.vivado import XilinxVivadoToolchain
-            if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
-                from migen.fhdl.simplify import FullMemoryWE
-                self.submodules.l2_cache = FullMemoryWE()(l2_cache)
-            else:
-                self.submodules.l2_cache = l2_cache
+            self.submodules.l2_cache = wishbone.Cache(
+                self.l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width))
             self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
 
     def do_finalize(self):