From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Aug 2014 14:41:27 +0000 (+0200)
Subject: Also allow "module foobar(input foo, output bar, ...);" syntax
X-Git-Tag: yosys-0.4~296
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2dc33337346ea53a654af3d80bdf056c7ccfa43c;p=yosys.git

Also allow "module foobar(input foo, output bar, ...);" syntax
---

diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index 95d7f3935..f619d3c2b 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -247,8 +247,7 @@ single_module_para:
 	};
 
 module_args_opt:
-	'(' ')' | /* empty */ | '(' module_args optional_comma ')' |
-	'(' '.' '.' '.' ')' { do_not_require_port_stubs = true; };
+	'(' ')' | /* empty */ | '(' module_args optional_comma ')';
 
 module_args:
 	module_arg | module_args ',' module_arg;
@@ -297,7 +296,10 @@ module_arg:
 		ast_stack.back()->children.push_back(node);
 		append_attr(node, $1);
 		delete $4;
-	} module_arg_opt_assignment;
+	} module_arg_opt_assignment |
+	'.' '.' '.' {
+		do_not_require_port_stubs = true;
+	};
 
 wire_type:
 	{