From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 11 Sep 2012 08:00:03 +0000 (+0200)
Subject: fhdl/verilog: sort clock domains by name
X-Git-Tag: 24jan2021_ls180~2099^2~835
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e14569b5c640d11e2b51a9aead9c1dfb134569e;p=litex.git

fhdl/verilog: sort clock domains by name
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 8993300e..d0cbecf8 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -1,4 +1,5 @@
 from functools import partial
+from operator import itemgetter
 
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign
@@ -171,7 +172,7 @@ def _printcomb(f, ns, display_run):
 
 def _printsync(f, ns, clock_domains):
 	r = ""
-	for k, v in f.sync.items():
+	for k, v in sorted(f.sync.items(), key=itemgetter(0)):
 		r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n"
 		r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v))
 		r += "end\n\n"