From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 2 Oct 2021 12:21:15 +0000 (+0100)
Subject: remove accidentally-added autogenerated file
X-Git-Tag: opf_rfc_ls005_v1~3784
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e2be85b12d60c2f3d456e4431372bd4bb87ebb2;p=libreriscv.git

remove accidentally-added autogenerated file
---

diff --git a/task_db/mdwn/cole.mdwn b/task_db/mdwn/cole.mdwn
deleted file mode 100644
index 77f01e259..000000000
--- a/task_db/mdwn/cole.mdwn
+++ /dev/null
@@ -1,73 +0,0 @@
-<!-- autogenerated by budget-sync -->
-
-# Cole Poirier
-
-
-
-# Status Tracking
-
-
-## Currently working on
-
-* [Bug #340](https://bugs.libre-soc.org/show_bug.cgi?id=340):
-  formal proof of POWER9 SHIFTROT pipeline needed
-* [Bug #448](https://bugs.libre-soc.org/show_bug.cgi?id=448):
-  MUL pipeline unit tests
-* [Bug #450](https://bugs.libre-soc.org/show_bug.cgi?id=450):
-  Create MMU from microwatt mmu\.vhdl
-
-## Completed but not yet paid
-
-
-## Paid by NLNet
-
-
-### NLNet.2019.10.Wishbone
-
-* [Bug #325](https://bugs.libre-soc.org/show_bug.cgi?id=325):
-  create POWER9 TRAP pipeline
-    * submitted on 2020-09-20
-    * paid on 2020-10-01
-    * &euro;100 out of total of &euro;500
-* [Bug #351](https://bugs.libre-soc.org/show_bug.cgi?id=351):
-  create a "block" \(mass\) regfile port \(read and write\) onto an array\-based regfile
-    * submitted on 2020-09-20
-    * paid on 2020-10-01
-    * &euro;100 out of total of &euro;200
-* [Bug #401](https://bugs.libre-soc.org/show_bug.cgi?id=401):
-  Convert Memory Architecture diagram from hand\-drawn to editable SVG
-    * submitted on 2020-09-20
-    * paid on 2020-10-01
-    * &euro;150 which is the total amount
-* [Bug #404](https://bugs.libre-soc.org/show_bug.cgi?id=404):
-  adding nmigen\-soc as a dependency needs documentation updated
-    * submitted on 2020-09-20
-    * paid on 2020-10-01
-    * &euro;100 which is the total amount
-* [Bug #472](https://bugs.libre-soc.org/show_bug.cgi?id=472):
-  tutorial and dev page needed for mesa driver
-    * submitted on 2020-09-20
-    * paid on 2020-10-01
-    * &euro;100 which is the total amount
-* [Bug #493](https://bugs.libre-soc.org/show_bug.cgi?id=493):
-  DMI JTAG TAP needed
-    * submitted on 2021-04-25
-    * paid on 2021-05-05
-    * &euro;150 out of total of &euro;400
-
-### NLNet.2019.Coriolis2
-
-* [Bug #178](https://bugs.libre-soc.org/show_bug.cgi?id=178):
-  first coriolis2 tutorial, workflow and "test project" page
-    * paid on 2020-12-20
-    * &euro;500 out of total of &euro;3000
-* [Bug #291](https://bugs.libre-soc.org/show_bug.cgi?id=291):
-  HDL Workflow and Coriolis2 chroot automated setup scripts
-    * submitted on 2020-09-20
-    * paid on 2020-10-01
-    * &euro;200 which is the total amount
-* [Bug #502](https://bugs.libre-soc.org/show_bug.cgi?id=502):
-  determine SRAM block size and implement it
-    * submitted on 2021-04-25
-    * paid on 2021-05-05
-    * &euro;50 out of total of &euro;1250