From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Jun 2020 12:28:35 +0000 (+0100)
Subject: expand Memory width to 64 and granularity to 16 in SRAM test
X-Git-Tag: div_pipeline~301
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e2e45c69adfa4e395a760f7d72d6a8179eabd6a;p=soc.git

expand Memory width to 64 and granularity to 16 in SRAM test
---

diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py
index dfebb3b8..d1a6d63a 100644
--- a/src/soc/bus/test/test_sram_wishbone.py
+++ b/src/soc/bus/test/test_sram_wishbone.py
@@ -5,8 +5,8 @@ Bugs:
 from nmigen_soc.wishbone.sram import SRAM
 from nmigen import Memory, Signal, Module
 
-memory = Memory(width=32, depth=16)
-sram = SRAM(memory=memory,granularity=8)
+memory = Memory(width=64, depth=16)
+sram = SRAM(memory=memory, granularity=16)
 
 # valid wishbone signals include
 # sram.bus.adr