From: Jonathan Marek Date: Sat, 11 Jul 2020 17:03:41 +0000 (-0400) Subject: freedreno/regs: update a6xx VPC regs X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e32a20f7c7ecf920968f1dffba713d47051ffb5;p=mesa.git freedreno/regs: update a6xx VPC regs Update some registers in the 0x9000-0x95ff range. Signed-off-by: Jonathan Marek Part-of: --- diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml index ab830373072..b03bd3f327c 100644 --- a/src/freedreno/registers/a6xx.xml +++ b/src/freedreno/registers/a6xx.xml @@ -1620,13 +1620,6 @@ to upconvert to 32b float internally? - - - - - - - @@ -2636,7 +2629,10 @@ to upconvert to 32b float internally? - + + + + @@ -2653,18 +2649,18 @@ to upconvert to 32b float internally? - + - + - + @@ -2673,8 +2669,8 @@ to upconvert to 32b float internally? - - + + @@ -2682,9 +2678,11 @@ to upconvert to 32b float internally? + + @@ -2696,26 +2694,26 @@ to upconvert to 32b float internally? + - + - - - - + + + + - - - + + - + - + @@ -2726,6 +2724,7 @@ to upconvert to 32b float internally? + @@ -2740,20 +2739,33 @@ to upconvert to 32b float internally? + + - - + + + - - - - + + + + + + + + + + + + + + diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index cbfc7dcebcc..c7c6df49a3f 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -592,8 +592,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd, tu6_emit_window_scissor(cs, x1, y1, x2, y2); tu6_emit_window_offset(cs, x1, y1); - tu_cs_emit_regs(cs, - A6XX_VPC_SO_OVERRIDE(.so_disable = false)); + tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); if (use_hw_binning(cmd)) { tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0); @@ -785,12 +784,10 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9107, 0); - tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9236, - A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0)); + tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false)); tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0); - tu_cs_emit_write_reg(cs, REG_A6XX_VPC_SO_OVERRIDE, - A6XX_VPC_SO_OVERRIDE_SO_DISABLE); + tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true)); tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0); tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0); @@ -1171,8 +1168,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_emit_cache_flush_ccu(cmd, cs, TU_CMD_CCU_SYSMEM); /* enable stream-out, with sysmem there is only one pass: */ - tu_cs_emit_regs(cs, - A6XX_VPC_SO_OVERRIDE(.so_disable = false)); + tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1); tu_cs_emit(cs, 0x1); @@ -1218,7 +1214,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) const struct tu_framebuffer *fb = cmd->state.framebuffer; if (use_hw_binning(cmd)) { /* enable stream-out during binning pass: */ - tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false)); + tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000); @@ -1228,7 +1224,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu6_emit_binning_pass(cmd, cs); /* and disable stream-out for draw pass: */ - tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=true)); + tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true)); tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000); @@ -1244,7 +1240,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit(cs, 0x1); } else { /* no binning pass, so enable stream-out for draw pass:: */ - tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(.so_disable=false)); + tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false)); tu6_emit_bin_size(cs, fb->tile0.width, fb->tile0.height, 0x6000000); } diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index d0734653f09..249fd632a9a 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -2235,7 +2235,7 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder, .vp_clip_code_ignore = 1)); tu_cs_emit_regs(&cs, - A6XX_VPC_POLYGON_MODE(.mode = mode)); + A6XX_VPC_POLYGON_MODE(mode)); tu_cs_emit_regs(&cs, A6XX_PC_POLYGON_MODE(.mode = mode)); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c index 09085b6adf4..2260f17b6a1 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c @@ -1184,11 +1184,11 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) WRITE(REG_A6XX_RB_UNKNOWN_881E, 0); WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0); - WRITE(REG_A6XX_VPC_UNKNOWN_9236, - A6XX_VPC_UNKNOWN_9236_POINT_COORD_INVERT(0)); + WRITE(REG_A6XX_VPC_POINT_COORD_INVERT, + A6XX_VPC_POINT_COORD_INVERT(0).value); WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0); - WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE_SO_DISABLE); + WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value); WRITE(REG_A6XX_PC_UNKNOWN_9990, 0); WRITE(REG_A6XX_PC_UNKNOWN_9980, 0); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c index 8e7ba94a05b..a07e02c4af5 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c @@ -705,8 +705,7 @@ fd6_emit_tile_init(struct fd_batch *batch) if (use_hw_binning(batch)) { /* enable stream-out during binning pass: */ - OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1); - OUT_RING(ring, 0); + OUT_REG(ring, A6XX_VPC_SO_DISABLE(false)); set_bin_size(ring, gmem->bin_w, gmem->bin_h, A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000); @@ -714,8 +713,7 @@ fd6_emit_tile_init(struct fd_batch *batch) emit_binning_pass(batch); /* and disable stream-out for draw pass: */ - OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1); - OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE); + OUT_REG(ring, A6XX_VPC_SO_DISABLE(true)); /* * NOTE: even if we detect VSC overflow and disable use of @@ -742,8 +740,7 @@ fd6_emit_tile_init(struct fd_batch *batch) OUT_RING(ring, 0x1); } else { /* no binning pass, so enable stream-out for draw pass:: */ - OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1); - OUT_RING(ring, 0); + OUT_REG(ring, A6XX_VPC_SO_DISABLE(false)); set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000); } @@ -1406,8 +1403,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass); /* enable stream-out, with sysmem there is only one pass: */ - OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1); - OUT_RING(ring, 0); + OUT_REG(ring, A6XX_VPC_SO_DISABLE(false)); OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1); OUT_RING(ring, 0x1); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c index 4d9ecf27b85..692e14ed48d 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c @@ -107,7 +107,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, break; } - OUT_REG(ring, A6XX_VPC_POLYGON_MODE(.mode = mode)); + OUT_REG(ring, A6XX_VPC_POLYGON_MODE(mode)); OUT_REG(ring, A6XX_PC_POLYGON_MODE(.mode = mode)); return ring;