From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 19 Oct 2018 11:05:51 +0000 (+0200)
Subject: Merge pull request #671 from rafaeltp/master
X-Git-Tag: yosys-0.9~437
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e32d05eabd1cf809fc01508be1951edad0680bf;p=yosys.git

Merge pull request #671 from rafaeltp/master

adding offset info to memories on verilog output
---

2e32d05eabd1cf809fc01508be1951edad0680bf