From: Luke Kenneth Casson Leighton Date: Wed, 5 Aug 2020 10:07:15 +0000 (+0000) Subject: substitute/indent to reduce to 80 char limit X-Git-Tag: partial-core-ls180-gdsii~99 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e49d22d4bc0e32b292443206b4ecbad2a709aba;p=soclayout.git substitute/indent to reduce to 80 char limit add first div (TODO) --- diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 2aca99e..754bc67 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -17,107 +17,160 @@ from plugins.alpha.block.configuration import IoPin af = CRL.AllianceFramework.get() +def find def scriptMain ( **kw ): """The mandatory function that Coriolis CGT/Unicorn will look for.""" global af + IW = IoPin.WEST + IE = IoPin.EAST + IS = IoPin.SOUTH + IN = IoPin.NORTH + AB = IoPin.A_BEGIN + AE = IoPin.A_END + + alup=[ + (IW | AB, 'clk' , 0 ), + (IW | AB, 'cu_issue_i' , 0 ), + (IW | AB, 'oper_i_alu_alu0_imm_data_imm_ok' , 0 ), + (IW | AB, 'oper_i_alu_alu0_invert_a' , 0 ), + (IW | AB, 'oper_i_alu_alu0_invert_out' , 0 ), + (IW | AB, 'oper_i_alu_alu0_is_32bit' , 0 ), + (IW | AB, 'oper_i_alu_alu0_is_signed' , 0 ), + (IW | AB, 'oper_i_alu_alu0_oe_oe' , 0 ), + (IW | AB, 'oper_i_alu_alu0_oe_oe_ok' , 0 ), + (IW | AB, 'oper_i_alu_alu0_output_carry' , 0 ), + (IW | AB, 'oper_i_alu_alu0_rc_rc' , 0 ), + (IW | AB, 'oper_i_alu_alu0_rc_rc_ok' , 0 ), + (IW | AB, 'oper_i_alu_alu0_write_cr0' , 0 ), + (IW | AB, 'oper_i_alu_alu0_zero_a' , 0 ), + (IW | AB, 'rst' , 0 ), + (IW | AB, 'src3_i' , 0 ), + (IW | AB, 'oper_i_alu_alu0_input_carry({})' , 0, l( 10.0), 2), + (IW | AB, 'src4_i({})' , 0, l( 10.0), 2), + (IW | AB, 'oper_i_alu_alu0_data_len({})' , 0, l( 10.0), 4), + (IW | AB, 'cu_rd_go_i({})' , 0, l( 10.0), 4), + (IW | AB, 'cu_rdmaskn_i({})' , 0, l( 10.0), 4), + (IW | AB, 'cu_wr_go_i({})' , 0, l( 10.0), 5), + (IW | AB, 'oper_i_alu_alu0_insn_type({})' , 0, l( 10.0), 7), + (IW | AB, 'oper_i_alu_alu0_fn_unit({})' , 0, l( 10.0), 11), + (IW | AB, 'oper_i_alu_alu0_insn({})' , 0, l( 10.0), 32), + (IW | AB, 'oper_i_alu_alu0_imm_data_imm({})', 0, l( 15.0), 64), + (IS , 'src1_i({})' , l(10), l( 15.0), 64), + (IS , 'src2_i({})' , l(15), l( 15.0), 64), + (IN , 'dest1_o({})' , l(20), l( 15.0), 64), + (IE | AE , 'cu_busy_o' , 0 ), + (IE | AE , 'cr_a_ok' , 0 ), + (IE | AE , 'dest5_o' , 0 ), + (IE | AE , 'o_ok' , 0 ), + (IE | AE , 'xer_ca_ok' , 0 ), + (IE | AE , 'xer_ov_ok' , 0 ), + (IE | AE , 'xer_so_ok' , 0 ), + (IE | AE , 'dest3_o({})' , 0, l( 20.0), 2), + (IE | AE , 'dest4_o({})' , 0, l( 20.0), 2), + (IE | AE , 'dest2_o({})' , 0, l( 20.0), 4), + (IE | AE , 'cu_rd_rel_o({})' , 0, l( 20.0), 4), + (IE | AE , 'cu_wr_rel_o({})' , 0, l( 20.0), 5), + ] + rvalue = True try: helpers.setTraceLevel( 550 ) cell, editor = plugins.kwParseMain( **kw ) alu0 = af.getCell( 'alu0', CRL.Catalog.State.Views ) - blockAlu0 = Block.create \ - ( alu0 - , ioPins=[ (IoPin.WEST |IoPin.A_BEGIN, 'clk' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_imm_data_imm_ok' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_invert_a' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_invert_out' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_is_32bit' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_is_signed' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_oe_oe' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_oe_oe_ok' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_output_carry' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_rc_rc' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_rc_rc_ok' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_write_cr0' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_zero_a' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i' , 0 ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_input_carry({})' , 0, l( 10.0), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'src4_i({})' , 0, l( 10.0), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_data_len({})' , 0, l( 10.0), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})' , 0, l( 10.0), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})' , 0, l( 10.0), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})' , 0, l( 10.0), 5) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_insn_type({})' , 0, l( 10.0), 7) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_fn_unit({})' , 0, l( 10.0), 11) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_insn({})' , 0, l( 10.0), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_alu0_imm_data_imm({})', 0, l( 15.0), 64) - , (IoPin.SOUTH , 'src1_i({})' , l(10), l( 15.0), 64) - , (IoPin.SOUTH , 'src2_i({})' , l(15), l( 15.0), 64) - , (IoPin.NORTH , 'dest1_o({})' , l(20), l( 15.0), 64) - , (IoPin.EAST |IoPin.A_END , 'cu_busy_o' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'cr_a_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'dest5_o' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'o_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'xer_ca_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'xer_ov_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'xer_so_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'dest3_o({})' , 0, l( 20.0), 2) - , (IoPin.EAST |IoPin.A_END , 'dest4_o({})' , 0, l( 20.0), 2) - , (IoPin.EAST |IoPin.A_END , 'dest2_o({})' , 0, l( 20.0), 4) - , (IoPin.EAST |IoPin.A_END , 'cu_rd_rel_o({})' , 0, l( 20.0), 4) - , (IoPin.EAST |IoPin.A_END , 'cu_wr_rel_o({})' , 0, l( 20.0), 5) - ] - ) + blockAlu0 = Block.create (alu0, ioPins = alup) blockAlu0.state.cfg.etesian.spaceMargin = 0.05 blockAlu0.state.fixedHeight = l(5000) blockAlu0.state.useSpares = False #rvalue = blockAlu0.build() + divp=[ + (IN , 'clk' , l(4500.0) ), + (IW | AB, 'cu_issue_i' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_imm_data_imm_ok' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_invert_a' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_invert_out' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_is_32bit' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_is_signed' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_oe_oe' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_oe_oe_ok' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_rc_rc' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_rc_rc_ok' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_write_cr0' , 0, l(20) ), + (IW | AB, 'oper_i_alu_div0_zero_a' , 0, l(20) ), + (IW | AB, 'rst' , 0, l(20) ), + (IW | AB, 'src3_i' , 0, l(20) ), + (IW | AB, 'cu_rd_go_i({})' , 0, l(10.0), 3), + (IW | AB, 'cu_rdmaskn_i({})' , 0, l(10.0), 3), + (IW | AB, 'cu_wr_go_i({})' , 0, l(10.0), 4), + (IW | AB, 'oper_i_alu_div0_insn_type({})' , 0, l(10.0), 7), + (IW | AB, 'oper_i_alu_div0_fn_unit({})' , 0, l(10.0), 11), + (IW | AB, 'oper_i_alu_div0_insn({})' , 0, l(10.0), 32), + (IW | AB, 'oper_i_alu_div0_imm_data_imm({})', 0, l(15.0), 64), + (IS | AB, 'src1_i({})' , l(10.0), l(50.0), 64), + (IS | AB, 'src2_i({})' , l(20.0), l(50.0), 64), + (IE | AE , 'cu_busy_o' , 0 ), + (IE | AE , 'cr_a_ok' , 0 ), + (IE | AE , 'dest4_o' , 0 ), + (IE | AE , 'o_ok' , 0 ), + (IE | AE , 'xer_ov_ok' , 0 ), + (IE | AE , 'xer_so_ok' , 0 ), + (IE | AE , 'dest3_o({})' , 0, l( 20.0), 2), + (IE | AE , 'dest2_o({})' , 0, l( 20.0), 4), + (IE | AE , 'cu_rd_rel_o({})' , 0, l( 20.0), 3), + (IE | AE , 'cu_wr_rel_o({})' , 0, l( 20.0), 4), + (IN | AE , 'dest1_o({})' , 0, l( 30.0), 64), + ] + div0 = af.getCell( 'div0', CRL.Catalog.State.Views ) + blockDiv0 = Block.create ( div0 , ioPins=divp) + blockDiv0.state.cfg.etesian.uniformDensity = True + blockDiv0.state.cfg.etesian.spaceMargin = 0.10 + blockDiv0.state.cfg.katana.searchHalo = 1 + blockDiv0.state.fixedHeight = l(5000) + blockDiv0.state.useSpares = False + #rvalue = blockDiv0.build() + + mulp=[ + (IN , 'clk' , l(4500.0) ), + (IW | AB, 'cu_issue_i' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_imm_data_imm_ok' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_invert_a' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_invert_out' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_is_32bit' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_is_signed' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_oe_oe' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_oe_oe_ok' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_rc_rc' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_rc_rc_ok' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_write_cr0' , 0, l(20) ), + (IW | AB, 'oper_i_alu_mul0_zero_a' , 0, l(20) ), + (IW | AB, 'rst' , 0, l(20) ), + (IW | AB, 'src3_i' , 0, l(20) ), + (IW | AB, 'cu_rd_go_i({})' , 0, l(10.0), 3), + (IW | AB, 'cu_rdmaskn_i({})' , 0, l(10.0), 3), + (IW | AB, 'cu_wr_go_i({})' , 0, l(10.0), 4), + (IW | AB, 'oper_i_alu_mul0_insn_type({})' , 0, l(10.0), 7), + (IW | AB, 'oper_i_alu_mul0_fn_unit({})' , 0, l(10.0), 11), + (IW | AB, 'oper_i_alu_mul0_insn({})' , 0, l(10.0), 32), + (IW | AB, 'oper_i_alu_mul0_imm_data_imm({})', 0, l(15.0), 64), + (IS | AB, 'src1_i({})' , l(10.0), l(50.0), 64), + (IS | AB, 'src2_i({})' , l(20.0), l(50.0), 64), + (IE | AE , 'cu_busy_o' , 0 ), + (IE | AE , 'cr_a_ok' , 0 ), + (IE | AE , 'dest4_o' , 0 ), + (IE | AE , 'o_ok' , 0 ), + (IE | AE , 'xer_ov_ok' , 0 ), + (IE | AE , 'xer_so_ok' , 0 ), + (IE | AE , 'dest3_o({})' , 0, l( 20.0), 2), + (IE | AE , 'dest2_o({})' , 0, l( 20.0), 4), + (IE | AE , 'cu_rd_rel_o({})' , 0, l( 20.0), 3), + (IE | AE , 'cu_wr_rel_o({})' , 0, l( 20.0), 4), + (IN | AE , 'dest1_o({})' , 0, l( 30.0), 64), + ] mul0 = af.getCell( 'mul0', CRL.Catalog.State.Views ) - blockMul0 = Block.create \ - ( mul0 - , ioPins=[ (IoPin.NORTH , 'clk' , l(4500.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_imm_data_imm_ok' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_invert_a' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_invert_out' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_is_32bit' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_is_signed' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_oe_oe' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_oe_oe_ok' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_rc_rc' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_rc_rc_ok' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_write_cr0' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_zero_a' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i' , 0, l(20) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})' , 0, l(10.0), 3) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})' , 0, l(10.0), 3) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})' , 0, l(10.0), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_insn_type({})' , 0, l(10.0), 7) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_fn_unit({})' , 0, l(10.0), 11) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_insn({})' , 0, l(10.0), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_mul0_imm_data_imm({})', 0, l(15.0), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})' , l(10.0), l(50.0), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})' , l(20.0), l(50.0), 64) - , (IoPin.EAST |IoPin.A_END , 'cu_busy_o' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'cr_a_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'dest4_o' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'o_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'xer_ov_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'xer_so_ok' , 0 ) - , (IoPin.EAST |IoPin.A_END , 'dest3_o({})' , 0, l( 20.0), 2) - , (IoPin.EAST |IoPin.A_END , 'dest2_o({})' , 0, l( 20.0), 4) - , (IoPin.EAST |IoPin.A_END , 'cu_rd_rel_o({})' , 0, l( 20.0), 3) - , (IoPin.EAST |IoPin.A_END , 'cu_wr_rel_o({})' , 0, l( 20.0), 4) - , (IoPin.NORTH|IoPin.A_END , 'dest1_o({})' , 0, l( 30.0), 64) - ] - ) + blockMul0 = Block.create ( mul0 , ioPins=mulp) blockMul0.state.cfg.etesian.uniformDensity = True blockMul0.state.cfg.etesian.spaceMargin = 0.10 blockMul0.state.cfg.katana.searchHalo = 1 @@ -125,37 +178,36 @@ def scriptMain ( **kw ): blockMul0.state.useSpares = False #rvalue = blockMul0.build() + branchp=[ + (IN, 'clk' , l( 805.0) ), + (IW , 'cu_issue_i' , l( 30.0) ), + (IW , 'oper_i_alu_branch0_imm_data_imm_ok' , l( 40.0) ), + (IW , 'oper_i_alu_branch0_is_32bit' , l( 70.0) ), + (IW , 'oper_i_alu_branch0_lk' , l( 150.0) ), + (IW , 'rst' , l( 160.0) ), + (IW , 'src3_i({})' , l( 180.0), l( 10.0), 4), + (IW , 'cu_rd_go_i({})' , l( 270.0), l( 10.0), 3), + (IW , 'cu_rdmaskn_i({})' , l( 310.0), l( 10.0), 3), + (IW , 'cu_wr_go_i({})' , l( 350.0), l( 10.0), 3), + (IW , 'oper_i_alu_branch0_insn_type({})' , l( 400.0), l( 10.0), 7), + (IW , 'oper_i_alu_branch0_fn_unit({})' , l( 470.0), l( 10.0), 11), + (IW , 'oper_i_alu_branch0_insn({})' , l( 580.0), l( 10.0), 32), + (IW , 'oper_i_alu_branch0_imm_data_imm({})', l( 900.0), l( 10.0), 64), + (IW , 'oper_i_alu_branch0_cia({})' , l(1540.0), l( 10.0), 64), + (IS, 'src1_i({})' , l( 10.0), l( 20.0), 64), + (IS, 'src2_i({})' , l( 15.0), l( 20.0), 64), + (IE , 'cu_busy_o' , l(3500.0) ), + (IE , 'fast1_ok' , l(3520.0) ), + (IE , 'fast2_ok' , l(3540.0) ), + (IE , 'nia_ok' , l(3560.0) ), + (IE , 'dest2_o({})' , l(3580.0), l( 10.0), 64), + (IE , 'dest3_o({})' , l(4220.0), l( 10.0), 64), + (IE , 'cu_rd_rel_o({})' , l(4860.0), l( 20.0), 3), + (IE , 'cu_wr_rel_o({})' , l(4920.0), l( 20.0), 3), + (IN, 'dest1_o({})' , l( 500.0), l( 10.0), 64), + ] branch0 = af.getCell( 'branch0', CRL.Catalog.State.Views ) - blockBranch0 = Block.create \ - ( branch0 - , ioPins=[ (IoPin.NORTH, 'clk' , l( 805.0) ) - , (IoPin.WEST , 'cu_issue_i' , l( 30.0) ) - , (IoPin.WEST , 'oper_i_alu_branch0_imm_data_imm_ok' , l( 40.0) ) - , (IoPin.WEST , 'oper_i_alu_branch0_is_32bit' , l( 70.0) ) - , (IoPin.WEST , 'oper_i_alu_branch0_lk' , l( 150.0) ) - , (IoPin.WEST , 'rst' , l( 160.0) ) - , (IoPin.WEST , 'src3_i({})' , l( 180.0), l( 10.0), 4) - , (IoPin.WEST , 'cu_rd_go_i({})' , l( 270.0), l( 10.0), 3) - , (IoPin.WEST , 'cu_rdmaskn_i({})' , l( 310.0), l( 10.0), 3) - , (IoPin.WEST , 'cu_wr_go_i({})' , l( 350.0), l( 10.0), 3) - , (IoPin.WEST , 'oper_i_alu_branch0_insn_type({})' , l( 400.0), l( 10.0), 7) - , (IoPin.WEST , 'oper_i_alu_branch0_fn_unit({})' , l( 470.0), l( 10.0), 11) - , (IoPin.WEST , 'oper_i_alu_branch0_insn({})' , l( 580.0), l( 10.0), 32) - , (IoPin.WEST , 'oper_i_alu_branch0_imm_data_imm({})', l( 900.0), l( 10.0), 64) - , (IoPin.WEST , 'oper_i_alu_branch0_cia({})' , l(1540.0), l( 10.0), 64) - , (IoPin.SOUTH, 'src1_i({})' , l( 10.0), l( 20.0), 64) - , (IoPin.SOUTH, 'src2_i({})' , l( 15.0), l( 20.0), 64) - , (IoPin.EAST , 'cu_busy_o' , l(3500.0) ) - , (IoPin.EAST , 'fast1_ok' , l(3520.0) ) - , (IoPin.EAST , 'fast2_ok' , l(3540.0) ) - , (IoPin.EAST , 'nia_ok' , l(3560.0) ) - , (IoPin.EAST , 'dest2_o({})' , l(3580.0), l( 10.0), 64) - , (IoPin.EAST , 'dest3_o({})' , l(4220.0), l( 10.0), 64) - , (IoPin.EAST , 'cu_rd_rel_o({})' , l(4860.0), l( 20.0), 3) - , (IoPin.EAST , 'cu_wr_rel_o({})' , l(4920.0), l( 20.0), 3) - , (IoPin.NORTH, 'dest1_o({})' , l( 500.0), l( 10.0), 64) - ] - ) + blockBranch0 = Block.create ( branch0 , ioPins=branchp) blockBranch0.state.cfg.etesian.spaceMargin = 0.07 blockBranch0.state.fixedHeight = l(5000) blockBranch0.state.useSpares = False @@ -164,32 +216,32 @@ def scriptMain ( **kw ): cr0 = af.getCell( 'cr0', CRL.Catalog.State.Views ) blockCr0 = Block.create \ ( cr0 - , ioPins=[ (IoPin.NORTH, 'clk' , l( 805.0) ) - , (IoPin.WEST , 'cu_issue_i' , l( 30.0) ) - , (IoPin.WEST , 'oper_i_alu_cr0_read_cr_whole' , l( 40.0) ) - , (IoPin.WEST , 'oper_i_alu_cr0_write_cr_whole' , l( 70.0) ) - , (IoPin.WEST , 'rst' , l( 160.0) ) - , (IoPin.WEST , 'src4_i({})' , l( 180.0), l( 10.0), 4) - , (IoPin.WEST , 'src5_i({})' , l( 220.0), l( 10.0), 4) - , (IoPin.WEST , 'src6_i({})' , l( 260.0), l( 10.0), 4) - , (IoPin.WEST , 'cu_rd_go_i({})' , l( 300.0), l( 10.0), 6) - , (IoPin.WEST , 'cu_rdmaskn_i({})' , l( 360.0), l( 10.0), 6) - , (IoPin.WEST , 'cu_wr_go_i({})' , l( 420.0), l( 10.0), 3) - , (IoPin.WEST , 'oper_i_alu_cr0_insn_type({})' , l( 450.0), l( 10.0), 7) - , (IoPin.WEST , 'oper_i_alu_cr0_fn_unit({})' , l( 520.0), l( 10.0), 11) - , (IoPin.WEST , 'oper_i_alu_cr0_insn({})' , l( 630.0), l( 10.0), 32) - , (IoPin.SOUTH, 'src1_i({})' , l( 10.0), l( 10.0), 64) - , (IoPin.SOUTH, 'src2_i({})' , l( 15.0), l( 10.0), 64) - , (IoPin.EAST , 'src3_i({})' , l( 10.0), l( 20.0), 32) - , (IoPin.EAST , 'cu_busy_o' , l(4320.0) ) - , (IoPin.EAST , 'cr_a_ok' , l(4340.0) ) - , (IoPin.EAST , 'full_cr_ok' , l(4360.0) ) - , (IoPin.EAST , 'o_ok' , l(4380.0) ) - , (IoPin.EAST , 'dest2_o({})' , l(4400.0), l( 10.0), 32) - , (IoPin.EAST , 'dest3_o({})' , l(4720.0), l( 10.0), 4) - , (IoPin.EAST , 'cu_rd_rel_o({})' , l(4800.0), l( 20.0), 6) - , (IoPin.EAST , 'cu_wr_rel_o({})' , l(4920.0), l( 20.0), 3) - , (IoPin.NORTH, 'dest1_o({})' , l( 100.0), l( 10.0), 64) + , ioPins=[ (IN, 'clk' , l( 805.0) ) + , (IW , 'cu_issue_i' , l( 30.0) ) + , (IW , 'oper_i_alu_cr0_read_cr_whole' , l( 40.0) ) + , (IW , 'oper_i_alu_cr0_write_cr_whole' , l( 70.0) ) + , (IW , 'rst' , l( 160.0) ) + , (IW , 'src4_i({})' , l( 180.0), l( 10.0), 4) + , (IW , 'src5_i({})' , l( 220.0), l( 10.0), 4) + , (IW , 'src6_i({})' , l( 260.0), l( 10.0), 4) + , (IW , 'cu_rd_go_i({})' , l( 300.0), l( 10.0), 6) + , (IW , 'cu_rdmaskn_i({})' , l( 360.0), l( 10.0), 6) + , (IW , 'cu_wr_go_i({})' , l( 420.0), l( 10.0), 3) + , (IW , 'oper_i_alu_cr0_insn_type({})' , l( 450.0), l( 10.0), 7) + , (IW , 'oper_i_alu_cr0_fn_unit({})' , l( 520.0), l( 10.0), 11) + , (IW , 'oper_i_alu_cr0_insn({})' , l( 630.0), l( 10.0), 32) + , (IS, 'src1_i({})' , l( 10.0), l( 10.0), 64) + , (IS, 'src2_i({})' , l( 15.0), l( 10.0), 64) + , (IE , 'src3_i({})' , l( 10.0), l( 20.0), 32) + , (IE , 'cu_busy_o' , l(4320.0) ) + , (IE , 'cr_a_ok' , l(4340.0) ) + , (IE , 'full_cr_ok' , l(4360.0) ) + , (IE , 'o_ok' , l(4380.0) ) + , (IE , 'dest2_o({})' , l(4400.0), l( 10.0), 32) + , (IE , 'dest3_o({})' , l(4720.0), l( 10.0), 4) + , (IE , 'cu_rd_rel_o({})' , l(4800.0), l( 20.0), 6) + , (IE , 'cu_wr_rel_o({})' , l(4920.0), l( 20.0), 3) + , (IN, 'dest1_o({})' , l( 100.0), l( 10.0), 64) ] ) blockCr0.state.cfg.etesian.spaceMargin = 0.10 @@ -200,50 +252,50 @@ def scriptMain ( **kw ): ldst0 = af.getCell( 'ldst0', CRL.Catalog.State.Views ) blockLdst0 = Block.create \ ( ldst0 - , ioPins=[ (IoPin.NORTH , 'clk' , l(805.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_ad_go_i' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_addr_exc_o' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_addr_ok_o' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_ld_data_o_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_byte_reverse' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_imm_data_imm_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_is_32bit' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_is_signed' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_oe_oe' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_oe_oe_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_rc_rc' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_rc_rc_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_sign_extend' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_zero_a' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_st_go_i' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_ldst_mode({})' , 0, l(20), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})' , 0, l(20), 3) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})' , 0, l(20), 3) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})' , 0, l(20), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_data_len({})' , 0, l(20), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_insn_type({})' , 0, l(20), 7) - , (IoPin.WEST |IoPin.A_BEGIN, 'ldst_port0_ld_data_o({})' , 0, l(20), 64) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_ldst_ldst0_imm_data_imm({})' , 0, l(20), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})' , 0, l(5), 64) - , (IoPin.EAST |IoPin.A_END , 'src3_i({})' , 0, 0, 64) - , (IoPin.EAST |IoPin.A_END , 'cu_busy_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cu_ad_rel_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'ldst_port0_addr_i_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'ldst_port0_is_ld_i' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'ldst_port0_is_st_i' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'load_mem_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cu_st_rel_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'stwd_mem_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'ea({})' , 0, l(20), 64) - , (IoPin.EAST |IoPin.A_END , 'ldst_port0_st_data_i({})' , 0, l(20), 64) - , (IoPin.EAST |IoPin.A_END , 'cu_rd_rel_o({})' , 0, 0, 3) - , (IoPin.EAST |IoPin.A_END , 'cu_wr_rel_o({})' , 0, 0, 2) - , (IoPin.EAST |IoPin.A_END , 'ldst_port0_addr_i_95' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'ldst_port0_addr_i_{}' , 0, l(20), 64) - , (IoPin.NORTH|IoPin.A_END , 'o({})' , 0, 0, 64) + , ioPins=[ (IN , 'clk' , l(805.0) ) + , (IW | AB, 'cu_ad_go_i' , 0, l(20), 1) + , (IW | AB, 'cu_issue_i' , 0, l(20), 1) + , (IW | AB, 'ldst_port0_addr_exc_o' , 0, l(20), 1) + , (IW | AB, 'ldst_port0_addr_ok_o' , 0, l(20), 1) + , (IW | AB, 'ldst_port0_ld_data_o_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_byte_reverse' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_is_32bit' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_is_signed' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_oe_oe' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_oe_oe_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_rc_rc' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_rc_rc_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_sign_extend' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_zero_a' , 0, l(20), 1) + , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'cu_st_go_i' , 0, l(20), 1) + , (IW | AB, 'oper_i_ldst_ldst0_ldst_mode({})' , 0, l(20), 2) + , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 3) + , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 3) + , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 2) + , (IW | AB, 'oper_i_ldst_ldst0_data_len({})' , 0, l(20), 4) + , (IW | AB, 'oper_i_ldst_ldst0_insn_type({})' , 0, l(20), 7) + , (IW | AB, 'ldst_port0_ld_data_o({})' , 0, l(20), 64) + , (IW | AB, 'oper_i_ldst_ldst0_imm_data_imm({})' , 0, l(20), 64) + , (IS | AB, 'src1_i({})' , 0, l(10), 64) + , (IS | AB, 'src2_i({})' , 0, l(5), 64) + , (IE | AE , 'src3_i({})' , 0, 0, 64) + , (IE | AE , 'cu_busy_o' , 0, l(20), 1) + , (IE | AE , 'cu_ad_rel_o' , 0, l(20), 1) + , (IE | AE , 'ldst_port0_addr_i_ok' , 0, l(20), 1) + , (IE | AE , 'ldst_port0_is_ld_i' , 0, l(20), 1) + , (IE | AE , 'ldst_port0_is_st_i' , 0, l(20), 1) + , (IE | AE , 'load_mem_o' , 0, l(20), 1) + , (IE | AE , 'cu_st_rel_o' , 0, l(20), 1) + , (IE | AE , 'stwd_mem_o' , 0, l(20), 1) + , (IE | AE , 'ea({})' , 0, l(20), 64) + , (IE | AE , 'ldst_port0_st_data_i({})' , 0, l(20), 64) + , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 3) + , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 2) + , (IE | AE , 'ldst_port0_addr_i_95' , 0, l(20), 1) + , (IE | AE , 'ldst_port0_addr_i_{}' , 0, l(20), 64) + , (IN | AE , 'o({})' , 0, 0, 64) ] ) blockLdst0.state.cfg.etesian.uniformDensity = True @@ -258,41 +310,41 @@ def scriptMain ( **kw ): logical0 = af.getCell( 'logical0', CRL.Catalog.State.Views ) blockLogical0 = Block.create \ ( logical0 - , ioPins=[ (IoPin.NORTH , 'clk' , l(805.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_imm_data_imm_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_invert_a' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_invert_out' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_is_32bit' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_is_signed' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_oe_oe' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_oe_oe_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_output_carry' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_rc_rc' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_rc_rc_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_write_cr0' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_zero_a' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_input_carry({})' , 0, l(20), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})' , 0, l(20), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})' , 0, l(20), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})' , 0, l(20), 3) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_data_len({})' , 0, l(20), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_insn_type({})' , 0, l(20), 7) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_fn_unit({})' , 0, l(20), 11) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_insn({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_logical0_imm_data_imm({})', 0, l(20), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})' , 0, l(5), 64) - , (IoPin.EAST |IoPin.A_END , 'cu_busy_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cr_a_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'o_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'xer_ca_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cu_rd_rel_o({})' , 0, 0, 2) - , (IoPin.EAST |IoPin.A_END , 'cu_wr_rel_o({})' , 0, 0, 3) - , (IoPin.NORTH|IoPin.A_END , 'dest3_o({})' , 0, 0, 2) - , (IoPin.NORTH|IoPin.A_END , 'dest2_o({})' , 0, 0, 4) - , (IoPin.NORTH|IoPin.A_END , 'dest1_o({})' , 0, 0, 64) + , ioPins=[ (IN , 'clk' , l(805.0) ) + , (IW | AB, 'cu_issue_i' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_imm_data_imm_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_invert_a' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_invert_out' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_is_32bit' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_is_signed' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_oe_oe' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_oe_oe_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_output_carry' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_rc_rc' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_rc_rc_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_write_cr0' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_zero_a' , 0, l(20), 1) + , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_logical0_input_carry({})' , 0, l(20), 2) + , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 2) + , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 2) + , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 3) + , (IW | AB, 'oper_i_alu_logical0_data_len({})' , 0, l(20), 4) + , (IW | AB, 'oper_i_alu_logical0_insn_type({})' , 0, l(20), 7) + , (IW | AB, 'oper_i_alu_logical0_fn_unit({})' , 0, l(20), 11) + , (IW | AB, 'oper_i_alu_logical0_insn({})' , 0, l(20), 32) + , (IW | AB, 'oper_i_alu_logical0_imm_data_imm({})', 0, l(20), 64) + , (IS | AB, 'src1_i({})' , 0, l(10), 64) + , (IS | AB, 'src2_i({})' , 0, l(5), 64) + , (IE | AE , 'cu_busy_o' , 0, l(20), 1) + , (IE | AE , 'cr_a_ok' , 0, l(20), 1) + , (IE | AE , 'o_ok' , 0, l(20), 1) + , (IE | AE , 'xer_ca_ok' , 0, l(20), 1) + , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 2) + , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 3) + , (IN | AE , 'dest3_o({})' , 0, 0, 2) + , (IN | AE , 'dest2_o({})' , 0, 0, 4) + , (IN | AE , 'dest1_o({})' , 0, 0, 64) ] ) blockLogical0.state.cfg.etesian.uniformDensity = True @@ -305,40 +357,40 @@ def scriptMain ( **kw ): shiftrot0 = af.getCell( 'shiftrot0', CRL.Catalog.State.Views ) blockShiftrot0 = Block.create \ ( shiftrot0 - , ioPins=[ (IoPin.NORTH , 'clk' , l(805.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_imm_data_imm_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_input_cr' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_is_32bit' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_is_signed' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_oe_oe' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_oe_oe_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_output_carry' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_output_cr' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_rc_rc' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_rc_rc_ok' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_input_carry({})' , 0, l(20), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'src4_i({})' , 0, l(10), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})' , 0, l(20), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})' , 0, l(20), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})' , 0, l(20), 3) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_insn_type({})' , 0, l(20), 7) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_fn_unit({})' , 0, l(20), 11) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_insn({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_shift_rot0_imm_data_imm({})', 0, l(20), 64) - , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})' , 0, l(5), 64) - , (IoPin.EAST |IoPin.A_END , 'cu_busy_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cr_a_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'o_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'xer_ca_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cu_rd_rel_o({})' , 0, 0, 4) - , (IoPin.EAST |IoPin.A_END , 'cu_wr_rel_o({})' , 0, 0, 3) - , (IoPin.NORTH|IoPin.A_END , 'dest3_o({})' , 0, 0, 2) - , (IoPin.NORTH|IoPin.A_END , 'dest2_o({})' , 0, 0, 4) - , (IoPin.NORTH|IoPin.A_END , 'dest1_o({})' , 0, 0, 64) + , ioPins=[ (IN , 'clk' , l(805.0) ) + , (IW | AB, 'cu_issue_i' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_input_cr' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_is_32bit' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_is_signed' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_oe_oe' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_oe_oe_ok' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_output_carry' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_output_cr' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_rc_rc_ok' , 0, l(20), 1) + , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_shift_rot0_input_carry({})' , 0, l(20), 2) + , (IW | AB, 'src4_i({})' , 0, l(10), 2) + , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4) + , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 4) + , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 3) + , (IW | AB, 'oper_i_alu_shift_rot0_insn_type({})' , 0, l(20), 7) + , (IW | AB, 'oper_i_alu_shift_rot0_fn_unit({})' , 0, l(20), 11) + , (IW | AB, 'oper_i_alu_shift_rot0_insn({})' , 0, l(20), 32) + , (IW | AB, 'oper_i_alu_shift_rot0_imm_data_imm({})', 0, l(20), 64) + , (IW | AB, 'src3_i({})' , 0, l(10), 64) + , (IS | AB, 'src1_i({})' , 0, l(10), 64) + , (IS | AB, 'src2_i({})' , 0, l(5), 64) + , (IE | AE , 'cu_busy_o' , 0, l(20), 1) + , (IE | AE , 'cr_a_ok' , 0, l(20), 1) + , (IE | AE , 'o_ok' , 0, l(20), 1) + , (IE | AE , 'xer_ca_ok' , 0, l(20), 1) + , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 4) + , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 3) + , (IN | AE , 'dest3_o({})' , 0, 0, 2) + , (IN | AE , 'dest2_o({})' , 0, 0, 4) + , (IN | AE , 'dest1_o({})' , 0, 0, 64) ] ) blockShiftrot0.state.cfg.etesian.uniformDensity = True @@ -351,37 +403,37 @@ def scriptMain ( **kw ): spr0 = af.getCell( 'spr0', CRL.Catalog.State.Views ) blockSpr0 = Block.create \ ( spr0 - , ioPins=[ (IoPin.NORTH , 'clk' , l(805.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_is_32bit' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'src4_i' , 0, l(10), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'src5_i({})' , 0, l(10), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'src6_i({})' , 0, l(10), 2) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})' , 0, l(20), 6) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})' , 0, l(20), 6) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})' , 0, l(20), 6) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_insn_type({})', 0, l(20), 7) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_fn_unit({})' , 0, l(20), 11) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_spr0_insn({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})' , 0, l(5), 64) - , (IoPin.EAST |IoPin.A_END , 'cu_busy_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'dest4_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'fast1_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'o_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'spr1_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'xer_ca_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'xer_ov_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'xer_so_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cu_rd_rel_o({})' , 0, 0, 6) - , (IoPin.EAST |IoPin.A_END , 'cu_wr_rel_o({})' , 0, 0, 6) - , (IoPin.NORTH|IoPin.A_END , 'dest5_o({})' , 0, 0, 2) - , (IoPin.NORTH|IoPin.A_END , 'dest6_o({})' , 0, 0, 2) - , (IoPin.EAST |IoPin.A_END , 'dest3_o({})' , 0, l(20), 64) - , (IoPin.EAST |IoPin.A_END , 'dest2_o({})' , 0, l(20), 64) - , (IoPin.EAST |IoPin.A_END , 'dest1_o({})' , 0, l(20), 64) + , ioPins=[ (IN , 'clk' , l(805.0) ) + , (IW | AB, 'cu_issue_i' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_spr0_is_32bit' , 0, l(20), 1) + , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'src4_i' , 0, l(10), 1) + , (IW | AB, 'src5_i({})' , 0, l(10), 2) + , (IW | AB, 'src6_i({})' , 0, l(10), 2) + , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 6) + , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 6) + , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 6) + , (IW | AB, 'oper_i_alu_spr0_insn_type({})', 0, l(20), 7) + , (IW | AB, 'oper_i_alu_spr0_fn_unit({})' , 0, l(20), 11) + , (IW | AB, 'oper_i_alu_spr0_insn({})' , 0, l(20), 32) + , (IW | AB, 'src3_i({})' , 0, l(10), 64) + , (IS | AB, 'src1_i({})' , 0, l(10), 64) + , (IS | AB, 'src2_i({})' , 0, l(5), 64) + , (IE | AE , 'cu_busy_o' , 0, l(20), 1) + , (IE | AE , 'dest4_o' , 0, l(20), 1) + , (IE | AE , 'fast1_ok' , 0, l(20), 1) + , (IE | AE , 'o_ok' , 0, l(20), 1) + , (IE | AE , 'spr1_ok' , 0, l(20), 1) + , (IE | AE , 'xer_ca_ok' , 0, l(20), 1) + , (IE | AE , 'xer_ov_ok' , 0, l(20), 1) + , (IE | AE , 'xer_so_ok' , 0, l(20), 1) + , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 6) + , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 6) + , (IN | AE , 'dest5_o({})' , 0, 0, 2) + , (IN | AE , 'dest6_o({})' , 0, 0, 2) + , (IE | AE , 'dest3_o({})' , 0, l(20), 64) + , (IE | AE , 'dest2_o({})' , 0, l(20), 64) + , (IE | AE , 'dest1_o({})' , 0, l(20), 64) ] ) blockSpr0.state.cfg.etesian.uniformDensity = True @@ -394,37 +446,37 @@ def scriptMain ( **kw ): trap0 = af.getCell( 'trap0', CRL.Catalog.State.Views ) blockTrap0 = Block.create \ ( trap0 - , ioPins=[ (IoPin.NORTH , 'clk' , l(805.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_issue_i' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_is_32bit' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rd_go_i({})' , 0, l(20), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_rdmaskn_i({})' , 0, l(20), 4) - , (IoPin.WEST |IoPin.A_BEGIN, 'cu_wr_go_i({})' , 0, l(20), 5) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_traptype({})' , 0, l(20), 5) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_insn_type({})', 0, l(20), 7) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_fn_unit({})' , 0, l(20), 11) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_trapaddr({})' , 0, l(20), 13) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_insn({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_cia({})' , 0, l(20), 64) - , (IoPin.WEST |IoPin.A_BEGIN, 'oper_i_alu_trap0_msr({})' , 0, l(20), 64) - , (IoPin.WEST |IoPin.A_BEGIN, 'src3_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src4_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src1_i({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'src2_i({})' , 0, l(5), 64) - , (IoPin.EAST |IoPin.A_END , 'cu_busy_o' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'fast1_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'fast2_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'msr_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'nia_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'o_ok' , 0, l(20), 1) - , (IoPin.EAST |IoPin.A_END , 'cu_rd_rel_o({})' , 0, 0, 4) - , (IoPin.EAST |IoPin.A_END , 'cu_wr_rel_o({})' , 0, 0, 5) - , (IoPin.NORTH|IoPin.A_END , 'dest5_o({})' , 0, l(10), 64) - , (IoPin.NORTH|IoPin.A_END , 'dest4_o({})' , 0, l(10), 64) - , (IoPin.EAST |IoPin.A_END , 'dest3_o({})' , 0, l(10), 64) - , (IoPin.EAST |IoPin.A_END , 'dest2_o({})' , 0, l(10), 64) - , (IoPin.EAST |IoPin.A_END , 'dest1_o({})' , 0, l(10), 64) + , ioPins=[ (IN , 'clk' , l(805.0) ) + , (IW | AB, 'cu_issue_i' , 0, l(20), 1) + , (IW | AB, 'oper_i_alu_trap0_is_32bit' , 0, l(20), 1) + , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 4) + , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 4) + , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 5) + , (IW | AB, 'oper_i_alu_trap0_traptype({})' , 0, l(20), 5) + , (IW | AB, 'oper_i_alu_trap0_insn_type({})', 0, l(20), 7) + , (IW | AB, 'oper_i_alu_trap0_fn_unit({})' , 0, l(20), 11) + , (IW | AB, 'oper_i_alu_trap0_trapaddr({})' , 0, l(20), 13) + , (IW | AB, 'oper_i_alu_trap0_insn({})' , 0, l(20), 32) + , (IW | AB, 'oper_i_alu_trap0_cia({})' , 0, l(20), 64) + , (IW | AB, 'oper_i_alu_trap0_msr({})' , 0, l(20), 64) + , (IW | AB, 'src3_i({})' , 0, l(10), 64) + , (IS | AB, 'src4_i({})' , 0, l(10), 64) + , (IS | AB, 'src1_i({})' , 0, l(10), 64) + , (IS | AB, 'src2_i({})' , 0, l(5), 64) + , (IE | AE , 'cu_busy_o' , 0, l(20), 1) + , (IE | AE , 'fast1_ok' , 0, l(20), 1) + , (IE | AE , 'fast2_ok' , 0, l(20), 1) + , (IE | AE , 'msr_ok' , 0, l(20), 1) + , (IE | AE , 'nia_ok' , 0, l(20), 1) + , (IE | AE , 'o_ok' , 0, l(20), 1) + , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 4) + , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 5) + , (IN | AE , 'dest5_o({})' , 0, l(10), 64) + , (IN | AE , 'dest4_o({})' , 0, l(10), 64) + , (IE | AE , 'dest3_o({})' , 0, l(10), 64) + , (IE | AE , 'dest2_o({})' , 0, l(10), 64) + , (IE | AE , 'dest1_o({})' , 0, l(10), 64) ] ) blockTrap0.state.cfg.etesian.uniformDensity = True @@ -437,26 +489,26 @@ def scriptMain ( **kw ): fast = af.getCell( 'fast', CRL.Catalog.State.Views ) blockFast = Block.create \ ( fast - , ioPins=[ (IoPin.NORTH , 'clk' , l(805.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'cia_ren({})' , 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'fast_nia_wen({})', 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'msr_ren({})' , 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'src1_ren({})' , 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'src2_ren({})' , 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'wen({})' , 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'wen_1({})' , 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'wen_3({})' , 0, l(20), 8) - , (IoPin.WEST |IoPin.A_BEGIN, 'wen_6({})' , 0, l(20), 8) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i({})' , 0, l(20), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_2({})' , 0, l(20), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_4({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_5({})' , 0, l(10), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_7({})' , 0, l(10), 64) - , (IoPin.NORTH|IoPin.A_END , 'cia_data_o({})' , 0, l(20), 64) - , (IoPin.NORTH|IoPin.A_END , 'msr_data_o({})' , 0, l(10), 64) - , (IoPin.NORTH|IoPin.A_END , 'src1_data_o({})' , 0, l(10), 64) - , (IoPin.NORTH|IoPin.A_END , 'src2_data_o({})' , 0, l(10), 64) + , ioPins=[ (IN , 'clk' , l(805.0) ) + , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'cia_ren({})' , 0, l(20), 8) + , (IW | AB, 'fast_nia_wen({})', 0, l(20), 8) + , (IW | AB, 'msr_ren({})' , 0, l(20), 8) + , (IW | AB, 'src1_ren({})' , 0, l(20), 8) + , (IW | AB, 'src2_ren({})' , 0, l(20), 8) + , (IW | AB, 'wen({})' , 0, l(20), 8) + , (IW | AB, 'wen_1({})' , 0, l(20), 8) + , (IW | AB, 'wen_3({})' , 0, l(20), 8) + , (IW | AB, 'wen_6({})' , 0, l(20), 8) + , (IS | AB, 'data_i({})' , 0, l(20), 64) + , (IS | AB, 'data_i_2({})' , 0, l(20), 64) + , (IS | AB, 'data_i_4({})' , 0, l(10), 64) + , (IS | AB, 'data_i_5({})' , 0, l(10), 64) + , (IS | AB, 'data_i_7({})' , 0, l(10), 64) + , (IN | AE , 'cia_data_o({})' , 0, l(20), 64) + , (IN | AE , 'msr_data_o({})' , 0, l(10), 64) + , (IN | AE , 'src1_data_o({})' , 0, l(10), 64) + , (IN | AE , 'src2_data_o({})' , 0, l(10), 64) ] ) blockFast.state.cfg.etesian.uniformDensity = True @@ -469,18 +521,18 @@ def scriptMain ( **kw ): cellInt = af.getCell( 'int', CRL.Catalog.State.Views ) blockInt = Block.create \ ( cellInt - , ioPins=[ (IoPin.NORTH , 'clk' , l(805.0) ) - , (IoPin.WEST |IoPin.A_BEGIN, 'rst' , 0, l(20), 1) - , (IoPin.WEST |IoPin.A_BEGIN, 'wen({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'wen_1({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'src1_ren({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'src2_ren({})' , 0, l(20), 32) - , (IoPin.WEST |IoPin.A_BEGIN, 'src3_ren({})' , 0, l(20), 32) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i({})' , 0, l(20), 64) - , (IoPin.SOUTH|IoPin.A_BEGIN, 'data_i_2({})' , 0, l(20), 64) - , (IoPin.NORTH|IoPin.A_END , 'src1_data_o({})' , 0, l(10), 64) - , (IoPin.NORTH|IoPin.A_END , 'src2_data_o({})' , 0, l(10), 64) - , (IoPin.NORTH|IoPin.A_END , 'src3_data_o({})' , 0, l(10), 64) + , ioPins=[ (IN , 'clk' , l(805.0) ) + , (IW | AB, 'rst' , 0, l(20), 1) + , (IW | AB, 'wen({})' , 0, l(20), 32) + , (IW | AB, 'wen_1({})' , 0, l(20), 32) + , (IW | AB, 'src1_ren({})' , 0, l(20), 32) + , (IW | AB, 'src2_ren({})' , 0, l(20), 32) + , (IW | AB, 'src3_ren({})' , 0, l(20), 32) + , (IS | AB, 'data_i({})' , 0, l(20), 64) + , (IS | AB, 'data_i_2({})' , 0, l(20), 64) + , (IN | AE , 'src1_data_o({})' , 0, l(10), 64) + , (IN | AE , 'src2_data_o({})' , 0, l(10), 64) + , (IN | AE , 'src3_data_o({})' , 0, l(10), 64) ] ) blockInt.state.cfg.etesian.uniformDensity = True