From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 9 Dec 2021 04:51:41 +0000 (-0800)
Subject: add initial ternlogi pseudo-code
X-Git-Tag: sv_maxu_works-initial~648
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e4fe2751bf7b3be37c67454e273722766cd2f64;p=openpower-isa.git

add initial ternlogi pseudo-code
---

diff --git a/openpower/isa/bitmanip.mdwn b/openpower/isa/bitmanip.mdwn
new file mode 100644
index 00000000..daa6e670
--- /dev/null
+++ b/openpower/isa/bitmanip.mdwn
@@ -0,0 +1,24 @@
+<!-- Draft Instructions here described in https://libre-soc.org/openpower/sv/bitmanip/ -->
+<!-- These instructions are *not yet official* -->
+
+# Ternary Bitwise Logic Immediate
+
+TLI-Form
+
+* ternlogi RT, RA, RB, TLI (Rc=0)
+* ternlogi. RT, RA, RB, TLI (Rc=1)
+
+Pseudo-code:
+
+    result <- [0] * XLEN
+    idx <- [0] * 3
+    do i = 0 to XLEN - 1
+      idx[0] <- (RT)[i]
+      idx[1] <- (RA)[i]
+      idx[2] <- (RB)[i]
+      result[i] <- (TLI & ROTL64(1, idx)) != 0
+    RT <- result
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
diff --git a/src/openpower/decoder/isa/.gitignore b/src/openpower/decoder/isa/.gitignore
index 5e256f88..6a07a25f 100644
--- a/src/openpower/decoder/isa/.gitignore
+++ b/src/openpower/decoder/isa/.gitignore
@@ -1,5 +1,6 @@
 /all.py
 /bcd.py
+/bitmanip.py
 /branch.py
 /comparefixed.py
 /condition.py