From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 9 Jun 2021 15:06:46 +0000 (+0100)
Subject: rename sys_clk to sys_pllclk
X-Git-Tag: DRAFT_SVP64_0_1~784
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e60a68e51d566f9193467e953a0901b3f66eb7c;p=libreriscv.git

rename sys_clk to sys_pllclk
---

diff --git a/180nm_Oct2020/ls180.mdwn b/180nm_Oct2020/ls180.mdwn
index 8a02f477e..7eec295d1 100644
--- a/180nm_Oct2020/ls180.mdwn
+++ b/180nm_Oct2020/ls180.mdwn
@@ -12,7 +12,7 @@ auto-generated by [[pinouts.py]]
 |   1 | N VDDE_2    |             |
 |   2 | N VDDI_12   |             |
 |   3 | N VSSI_12   |             |
-|  22 | N SYS_CLK   |             |
+|  22 | N SYS_PLLCLK |             |
 |  23 | N SYS_PLLSELA0 |             |
 |  24 | N SYS_PLLSELA1 |             |
 |  25 | N SYS_PLLTESTOUT |             |
@@ -240,7 +240,7 @@ SDRAM
 
 System Control
 
-* SYS_CLK   : N22/0
+* SYS_PLLCLK : N22/0
 * SYS_PLLSELA0 : N23/0
 * SYS_PLLSELA1 : N24/0
 * SYS_PLLTESTOUT : N25/0
@@ -363,7 +363,7 @@ GND
 
 
 
-* SYS_CLK 22 N22/0
+* SYS_PLLCLK 22 N22/0
 * SYS_PLLSELA0 23 N23/0
 * SYS_PLLSELA1 24 N24/0
 * SYS_PLLTESTOUT 25 N25/0