From: Tobias Platen <tplaten@posteo.de>
Date: Thu, 25 Nov 2021 16:53:42 +0000 (+0100)
Subject: mmu: add debug output
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e632c4f8bd3cff6236d9957797533b81a552f3b;p=soc.git

mmu: add debug output
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index 966bbad8..aadffaaa 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -33,6 +33,9 @@ from soc.experiment.mem_types import (LoadStore1ToMMUType,
                                  MMUToICacheType)
 
 
+# for debugging
+display_invalid = True
+
 @unique
 class State(Enum):
     IDLE = 0            # zero is default on reset for r.state
@@ -166,6 +169,9 @@ class MMU(Elaboratable):
                     # Use RPDS = 0 to disable radix tree walks
                     comb += v.state.eq(State.RADIX_FINISH)
                     comb += v.invalid.eq(1)
+                    if(display_invalid):
+                        sync += Display("MMUBUG: Use RPDS = 0 to disable"
+                                        " radix tree walks")
                 with m.Else():
                     comb += v.state.eq(State.SEGMENT_CHECK)
 
@@ -212,6 +218,7 @@ class MMU(Elaboratable):
         with m.Else():
             comb += v.state.eq(State.RADIX_FINISH)
             comb += v.invalid.eq(1)
+            if(display_invalid): m.d.sync += Display("MMUBUG: mbits is invalid")
 
     def radix_read_wait(self, m, v, r, d_in, data):
         comb = m.d.comb
@@ -278,6 +285,8 @@ class MMU(Elaboratable):
             # non-present PTE, generate a DSI
             comb += v.state.eq(State.RADIX_FINISH)
             comb += v.invalid.eq(1)
+            if(display_invalid):
+                sync += Display("MMUBUG: non-present PTE, generate a DSI")
 
     def segment_check(self, m, v, r, data, finalmask):
         comb = m.d.comb