From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 2 May 2020 16:56:10 +0000 (-0700)
Subject: tests: aiger test for wire->start_offset != 0
X-Git-Tag: working-ls180~576^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e78daf1ca68068ca9fa02eca1cc10e64d92cb11;p=yosys.git

tests: aiger test for wire->start_offset != 0
---

diff --git a/tests/aiger/neg.ys b/tests/aiger/neg.ys
new file mode 100644
index 000000000..4c1edd8a4
--- /dev/null
+++ b/tests/aiger/neg.ys
@@ -0,0 +1,36 @@
+read_verilog <<EOT
+module top(input [31:-32] a, input [-65:-128] b, output [128:65] c);
+assign c = a & b;
+endmodule
+EOT
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+design -save read
+
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_aiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
+
+
+design -load read
+!rm -rf neg.out
+!mkdir neg.out
+simplemap
+write_xaiger -map neg.out/neg.map neg.out/neg.aig
+
+design -reset
+read_aiger -wideports -map neg.out/neg.map neg.out/neg.aig
+select -assert-count 1 i:a
+select -assert-count 1 i:b
+select -assert-count 1 o:c
+select -assert-count 3 x:* s:64 %i
diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 8e932b091..de7bc68cf 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -52,3 +52,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports -seq 16 miter
 " -l ${aig}.log
 done
+
+for y in *.ys; do
+    echo "Running $y."
+    ../../yosys $y -ql ${y%.*}.log
+done