From: Luke Kenneth Casson Leighton Date: Fri, 9 Sep 2022 00:42:15 +0000 (+0100) Subject: clarify X-Git-Tag: opf_rfc_ls005_v1~577 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e812367d53775b4b2f85ca4a61a8d71b1d87eb1;p=libreriscv.git clarify --- diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 5def9f75a..096759343 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -79,22 +79,22 @@ to provide future expanded register file bitwidths and sizes. The fundamental principle of Simple-V is that it sits between Issue and Decode, pausing the Program-Counter to service a "Sub-Program-Counter" -hardware for-loop. In practical terms for many first-iteration +hardware for-loop. In practical terms for many first-version implementations this is sufficient. **Considerable** effort has been expended to ensure that Simple-V is practical to implement on an extremely wide range of Industry-wide common **Scalar** micro-architectures. Finite State Machine (for ultra-low-resource and Mission-Critical), In-order single-issue, all the -way through to Great-Big Out-of-Order Superscalar Multi-Issue, and the +way through to Great-Big Out-of-Order Superscalar Multi-Issue. The SV Compliancy Levels specifically recognise these differing scenarios. SIMD back-end ALUs particularly those with element-level predicate masks may be exploited to good effect with very little additional complexity to achieve high throughput, even on a single-issue in-order -microarchitecture. As usually becomes apparent with in-order, its +microarchitecture. As usually becomes quickly apparent with in-order, its limitations extend also to when Simple-V is deployed, which is why -Multi-Issue Out-of-Order is the recommended (but not mandatory) +Multi-Issue Out-of-Order is the recommended (but not mandatory) Scalar Micro-architecture. The only major concern is in the upper SV Compliancy Levels: the Hazard @@ -107,7 +107,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures. # Simple-V Architectural Resources * No new Interrupt types are required. - **No modifications to existing Power ISA are required either**. + (**No modifications to existing Power ISA are required either**). * GPR FPR and CR Field Register numbers are extended to 128. A future version may extend to 256 or beyond [^extend] * (A future version or other Stakeholder *may* wish to drop Simple-V