From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Jun 2020 12:45:01 +0000 (+0100)
Subject: bit of a mess.  getting carry recognised and output for shiftrot
X-Git-Tag: div_pipeline~318
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e85730b3f549508e7aeef8506eff3fa59f012b9;p=soc.git

bit of a mess.  getting carry recognised and output for shiftrot
was interfering with fixedarith carry "implicit" computation.
had to special-case this in pywriter.py and parser.py
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index e5d14652..79e8b13e 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -335,8 +335,16 @@ class ISACaller:
             imm = yield self.dec2.e.imm_data.data
             inputs.append(SelectableInt(imm, 64))
         assert len(outputs) >= 1
-        output = outputs[0]
-        gts = [(x > output) for x in inputs]
+        print ("outputs", repr(outputs))
+        if isinstance(outputs, list) or isinstance(outputs, tuple):
+            output = outputs[0]
+        else:
+            output = outputs
+        gts = []
+        for x in inputs:
+            print ("gt input", x, output)
+            gt = (x > output)
+            gts.append(gt)
         print(gts)
         cy = 1 if any(gts) else 0
         if not (1 & already_done):
@@ -344,8 +352,11 @@ class ISACaller:
 
         print ("inputs", inputs)
         # 32 bit carry
-        gts = [(x[32:64] > output[32:64]) == SelectableInt(1, 1)
-               for x in inputs]
+        gts = []
+        for x in inputs:
+            print ("input", x, output)
+            gt = (x[32:64] > output[32:64]) == SelectableInt(1, 1)
+            gts.append(gt)
         cy32 = 1 if any(gts) else 0
         if not (2 & already_done):
             self.spr['XER'][XER_bits['CA32']] = cy32
diff --git a/src/soc/decoder/power_pseudo.py b/src/soc/decoder/power_pseudo.py
index 67ae8bc8..e2b6440a 100644
--- a/src/soc/decoder/power_pseudo.py
+++ b/src/soc/decoder/power_pseudo.py
@@ -211,10 +211,10 @@ def tolist(num):
 def get_reg_hex(reg):
     return hex(reg.value)
 
-def convert_to_python(pcode, form):
+def convert_to_python(pcode, form, incl_carry):
 
     print ("form", form)
-    gsc = GardenSnakeCompiler(form=form)
+    gsc = GardenSnakeCompiler(form=form, incl_carry=incl_carry)
 
     tree = gsc.compile(pcode, mode="exec", filename="string")
     tree = ast.fix_missing_locations(tree)
diff --git a/src/soc/decoder/pseudo/parser.py b/src/soc/decoder/pseudo/parser.py
index 9b3e8f82..d92e43aa 100644
--- a/src/soc/decoder/pseudo/parser.py
+++ b/src/soc/decoder/pseudo/parser.py
@@ -240,7 +240,8 @@ class PowerParser:
         ("left", "INVERT"),
     )
 
-    def __init__(self, form):
+    def __init__(self, form, include_carry_in_write=False):
+        self.include_ca_in_write = include_carry_in_write
         self.gprs = {}
         form = self.sd.sigforms[form]
         print(form)
@@ -248,6 +249,7 @@ class PowerParser:
         self.declared_vars = set()
         for rname in ['RA', 'RB', 'RC', 'RT', 'RS']:
             self.gprs[rname] = None
+            self.declared_vars.add(rname)
         self.available_op_fields = set()
         for k in formkeys:
             if k not in self.gprs:
@@ -631,8 +633,9 @@ class PowerParser:
         name = p[1]
         if name in self.available_op_fields:
             self.op_fields.add(name)
-        if name in ['CA', 'CA32']:
-            self.write_regs.add(name)
+        if self.include_ca_in_write:
+            if name in ['CA', 'CA32']:
+                self.write_regs.add(name)
         if name in ['CR', 'LR', 'CTR', 'TAR', 'FPSCR', 'MSR']:
             self.special_regs.add(name)
             self.write_regs.add(name) # and add to list to write
@@ -795,9 +798,9 @@ class PowerParser:
 
 
 class GardenSnakeParser(PowerParser):
-    def __init__(self, lexer=None, debug=False, form=None):
+    def __init__(self, lexer=None, debug=False, form=None, incl_carry=False):
         self.sd = create_pdecode()
-        PowerParser.__init__(self, form)
+        PowerParser.__init__(self, form, incl_carry)
         self.debug = debug
         if lexer is None:
             lexer = IndentLexer(debug=0)
@@ -817,8 +820,9 @@ class GardenSnakeParser(PowerParser):
 #from compiler import misc, syntax, pycodegen
 
 class GardenSnakeCompiler(object):
-    def __init__(self, debug=False, form=None):
-        self.parser = GardenSnakeParser(debug=debug, form=form)
+    def __init__(self, debug=False, form=None, incl_carry=False):
+        self.parser = GardenSnakeParser(debug=debug, form=form,
+                                        incl_carry=incl_carry)
 
     def compile(self, code, mode="exec", filename="<string>"):
         tree = self.parser.parse(code)
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 88b7539d..f6c1ef6a 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -55,7 +55,8 @@ class PyISAWriter(ISA):
                 print (fname, d.opcode)
                 pcode = '\n'.join(d.pcode) + '\n'
                 print (pcode)
-                pycode, rused = convert_to_python(pcode, d.form)
+                incl_carry = page == 'fixedshift'
+                pycode, rused = convert_to_python(pcode, d.form, incl_carry)
                 # create list of arguments to call
                 regs = list(rused['read_regs']) + list(rused['uninit_regs'])
                 regs += list(rused['special_regs'])