From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 4 May 2020 19:18:02 +0000 (-0700)
Subject: test: add failing test
X-Git-Tag: working-ls180~557^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e911bc806d0a54e4d7e84ef2218ff088ea20b5f;p=yosys.git

test: add failing test
---

diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys
new file mode 100644
index 000000000..d87f4424e
--- /dev/null
+++ b/tests/verilog/upto.ys
@@ -0,0 +1,5 @@
+read_verilog <<EOT
+module top(input [-128:-65] a);
+endmodule
+EOT
+dump