From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 16:26:08 +0000 (-0700)
Subject: Do not simplemap for variable test
X-Git-Tag: working-ls180~1085^2~11
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2e9e745efa03363f9f0d5cc47696401d55a8e5d2;p=yosys.git

Do not simplemap for variable test
---

diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys
index 4e3c44a98..b8df0e55a 100644
--- a/tests/xilinx/xilinx_srl.ys
+++ b/tests/xilinx/xilinx_srl.ys
@@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test
 prep
 design -save gold
 
-simplemap t:$dff t:$dffe
 xilinx_srl -variable
 opt
 
 #stat
 # show -width
 # write_verilog -noexpr -norename
-select -assert-count 1 t:$_DFF_P_
+select -assert-count 1 t:$dff
+select -assert-count 1 t:$dff r:WIDTH=1 %i
 select -assert-count 2 t:$__XILINX_SHREG_
 
 design -stash gate