From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 1 Jul 2019 21:04:06 +0000 (-0700)
Subject: Fix $__XILINX_MUXF78 box timing
X-Git-Tag: working-ls180~1208^2~32
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ea6083b7ecea979838c2be40f5f7ef907f553d6;p=yosys.git

Fix $__XILINX_MUXF78 box timing
---

diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 273d36573..3789ff350 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -17,7 +17,7 @@ MUXF8 2 1 3 1
 # Inputs: I0 I1 I2 I3 S0 S1
 # Outputs: O
 $__MUXF78 3 1 6 1
-190 193 217 223 296 273
+294 297 311 317 390 273
 
 # CARRY4 + CARRY4_[ABCD]X
 # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI