From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Wed, 23 Feb 2011 21:10:50 +0000 (-0600)
Subject: ARM: Set ITSTATE correctly after FlushPipe
X-Git-Tag: stable_2012_02_02~530
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2eb19dac6506efa16cd39c2b64c85163f48ab1c1;p=gem5.git

ARM: Set ITSTATE correctly after FlushPipe
---

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index e388c72a8..9ce2e2da4 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -220,6 +220,7 @@ FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
     // start refetching from the next instruction.
     PCState pc = tc->pcState();
     assert(inst);
+    pc.forcedItState(inst->machInst.newItstate);
     inst->advancePC(pc);
     tc->pcState(pc);
 }