From: Anthony Gutierrez <atgutier@umich.edu>
Date: Fri, 27 Jul 2012 20:08:04 +0000 (-0400)
Subject: ARM: fix value of MISCREG_CTR returned by readMiscReg()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2eb6b403c976c7909a065b70ef831f4a309455b3;p=gem5.git

ARM: fix value of MISCREG_CTR returned by readMiscReg()

According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines)
[31:29] Format - b100 specifies v7
[28] RAZ - b0
[27:24] CWG log2(max writeback size #words) - 0x4 16 words
[23:20] ERG log2(max reservation size #words) - 0x4 16 words
[19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words
[15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT
[13:4] RAZ - b0000000000
[3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
---

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 2a5fbd2f0..b253574c7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -222,7 +222,33 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
       case MISCREG_ID_PFR1:
         return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
       case MISCREG_CTR:
-        return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
+        {
+            //all caches have the same line size in gem5
+            //4 byte words in ARM
+            unsigned lineSizeWords =
+                tc->getCpuPtr()->getInstPort().peerBlockSize() / 4;
+            unsigned log2LineSizeWords = 0;
+
+            while (lineSizeWords >>= 1) {
+                ++log2LineSizeWords;
+            }
+
+            CTR ctr = 0;
+            //log2 of minimun i-cache line size (words)
+            ctr.iCacheLineSize = log2LineSizeWords;
+            //b11 - gem5 uses pipt
+            ctr.l1IndexPolicy = 0x3;
+            //log2 of minimum d-cache line size (words)
+            ctr.dCacheLineSize = log2LineSizeWords;
+            //log2 of max reservation size (words)
+            ctr.erg = log2LineSizeWords;
+            //log2 of max writeback size (words)
+            ctr.cwg = log2LineSizeWords;
+            //b100 - gem5 format is ARMv7
+            ctr.format = 0x4;
+
+            return ctr;
+        }
       case MISCREG_ACTLR:
         warn("Not doing anything for miscreg ACTLR\n");
         break;
@@ -250,7 +276,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         /* For now just implement the version number.
          * Return 0 as we don't support debug architecture yet.
          */
-         return 0;
+        return 0;
       case MISCREG_DBGDSCR_INT:
         return 0;
     }
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 0969479ee..7af4ec605 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -529,6 +529,16 @@ namespace ArmISA
       Bitfield<31>    l2rstDISABLE_monitor;
    EndBitUnion(L2CTLR)
 
+   BitUnion32(CTR)
+      Bitfield<3,0>   iCacheLineSize;
+      Bitfield<13,4>  raz_13_4;
+      Bitfield<15,14> l1IndexPolicy;
+      Bitfield<19,16> dCacheLineSize;
+      Bitfield<23,20> erg;
+      Bitfield<27,24> cwg;
+      Bitfield<28>    raz_28;
+      Bitfield<31,29> format;
+   EndBitUnion(CTR)
 }
 
 #endif // __ARCH_ARM_MISCREGS_HH__