From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 1 Jun 2021 13:12:49 +0000 (+0100)
Subject: bit more memdump debugging on qemu sim
X-Git-Tag: xlen-bcd~499
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ec5391f2ea259273237f84c7a7ff2a0d8a40966;p=openpower-isa.git

bit more memdump debugging on qemu sim
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 427ad4ff..86446f03 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1233,7 +1233,7 @@ class ISACaller:
             self.last_st_addr = self.mem.last_st_addr
         if int_op in [MicrOp.OP_LOAD.value,
                      ]:
-            self.last_st_addr = self.mem.last_st_addr
+            self.last_ld_addr = self.mem.last_ld_addr
         log ("op", int_op, MicrOp.OP_STORE.value, MicrOp.OP_LOAD.value,
                    self.last_st_addr, self.last_ld_addr)
 
diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index 690f3eca..0f2ed5fc 100644
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -229,8 +229,9 @@ def run_tst(args, generator, qemu,
                 addr = simulator.last_st_addr & ~0x7 # align
                 sim_data = simulator.mem.ld(addr, 8, swap=False)
                 qdata = qemu.get_mem(addr, 8)[0]
-                log ("last st", simulator.last_st_addr, sim_data, qdata)
-                if sim_data !=qdata :
+                log ("last st", hex(simulator.last_st_addr),
+                                hex(sim_data), hex(qdata))
+                if sim_data != qdata:
                     log("expect mem %x, %x got %x" % (addr, qdata, sim_data))
             if _pc is None:
                 break
@@ -360,10 +361,13 @@ def run_simulation():
             write_data(simulator.mem, fname, offs, length)
             if qemu:
                 qmem = qemu.get_mem(offs, length)
+                log("qemu mem", hex(offs), length)
                 for i, mem in enumerate(qmem):
                     log(hex(offs+i*8), hex(mem))
-                for reg, val in qemu._get_registers().items():
-                    log ("qemu reg", reg, hex(val))
+        if qemu:
+            log("final complete qemu reg dump")
+            for reg, val in qemu._get_registers().items():
+                log ("qemu reg", reg, hex(val))
 
         # cleanup
         if qemu:
diff --git a/src/openpower/simulator/qemu.py b/src/openpower/simulator/qemu.py
index 4fbaecb1..9e1b6f6a 100644
--- a/src/openpower/simulator/qemu.py
+++ b/src/openpower/simulator/qemu.py
@@ -94,7 +94,7 @@ class QemuController:
     def get_mem(self, addr, nbytes):
         res = self.gdb.write("-data-read-memory %d u 1 1 %d" %
                              (addr, nbytes))
-        #print ("get_mem", res)
+        print ("get_mem", res)
         for x in res:
             if(x["type"] == "result"):
                 l = list(map(int, x['payload']['memory'][0]['data']))
diff --git a/src/test/basic_pypowersim/Makefile b/src/test/basic_pypowersim/Makefile
index bcce302c..1ec2e996 100644
--- a/src/test/basic_pypowersim/Makefile
+++ b/src/test/basic_pypowersim/Makefile
@@ -8,7 +8,10 @@ all: sim
 sim: kernel.bin
 	echo -n -e \\0060\\0000\\0061\\0000 > test.bin
 	echo -n -e \\0060\\0000\\0061\\0000 >> test.bin
-	pypowersim -q --load test.bin:0 -g gpr.list -i kernel.bin
+	pypowersim -q --load test.bin:0 \
+                  --dump testout.bin:0:8 \
+                  --dump testout2.bin:0x20000100:8 \
+                -g gpr.list -i kernel.bin
 
 clean:
 	rm *.o *.elf *.bin