From: Florent Kermarrec Date: Thu, 21 May 2020 07:06:29 +0000 (+0200) Subject: build/sim: rename dut to sim (for consistency with other builds). X-Git-Tag: 24jan2021_ls180~307 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2eea7864369af7e79994b19739b1ed56ae620b3c;p=litex.git build/sim: rename dut to sim (for consistency with other builds). --- diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile index 225ff0f2..5615fe3d 100644 --- a/litex/build/sim/core/Makefile +++ b/litex/build/sim/core/Makefile @@ -12,7 +12,7 @@ else endif -CC_SRCS ?= "--cc dut.v" +CC_SRCS ?= "--cc sim.v" SRC_DIR ?= . INC_DIR ?= . @@ -21,7 +21,7 @@ export OBJ_DIR = $(abspath obj_dir) SRCS_SIM_ABSPATH = $(wildcard $(SRC_DIR)/*.c) SRCS_SIM = $(notdir $(SRCS_SIM_ABSPATH)) -SRCS_SIM_CPP = dut_init.cpp $(SRC_DIR)/veril.cpp +SRCS_SIM_CPP = sim_init.cpp $(SRC_DIR)/veril.cpp OBJS_SIM = $(SRCS_SIM:.c=.o) all: modules sim @@ -34,10 +34,10 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c | mkdir .PHONY: sim sim: $(OBJS_SIM) | mkdir - verilator -Wno-fatal -O3 $(CC_SRCS) --top-module dut --exe \ + verilator -Wno-fatal -O3 $(CC_SRCS) --top-module sim --exe \ -DPRINTF_COND=0 \ $(SRCS_SIM_CPP) $(OBJS_SIM) \ - --top-module dut \ + --top-module sim \ $(if $(THREADS), --threads $(THREADS),) \ -CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \ -LDFLAGS "$(LDFLAGS)" \ @@ -48,7 +48,7 @@ sim: $(OBJS_SIM) | mkdir $(INC_DIR) \ -Wno-BLKANDNBLK \ -Wno-WIDTH - make -j -C $(OBJ_DIR) -f Vdut.mk Vdut + make -j -C $(OBJ_DIR) -f Vsim.mk Vsim .PHONY: modules modules: diff --git a/litex/build/sim/core/sim.c b/litex/build/sim/core/sim.c index 3f7ad648..a4e9adea 100644 --- a/litex/build/sim/core/sim.c +++ b/litex/build/sim/core/sim.c @@ -34,7 +34,7 @@ struct session_list_s { struct session_list_s *sesslist=NULL; struct event_base *base=NULL; -static int litex_sim_initialize_all(void **dut, void *base) +static int litex_sim_initialize_all(void **sim, void *base) { struct module_s *ml=NULL; struct module_s *mli=NULL; @@ -44,7 +44,7 @@ static int litex_sim_initialize_all(void **dut, void *base) struct pad_list_s *plist=NULL; struct pad_list_s *pplist=NULL; struct session_list_s *slist=NULL; - void *vdut=NULL; + void *vsim=NULL; int i; int ret = RC_OK; @@ -69,7 +69,7 @@ static int litex_sim_initialize_all(void **dut, void *base) goto out; } /* Init generated */ - litex_sim_init(&vdut); + litex_sim_init(&vsim); /* Get pads from generated */ ret = litex_sim_pads_get_list(&plist); @@ -134,7 +134,7 @@ static int litex_sim_initialize_all(void **dut, void *base) } } } - *dut = vdut; + *sim = vsim; out: return ret; } @@ -170,7 +170,7 @@ struct event *ev; static void cb(int sock, short which, void *arg) { struct session_list_s *s; - void *vdut=arg; + void *vsim=arg; struct timeval tv; tv.tv_sec = 0; tv.tv_usec = 0; @@ -183,7 +183,7 @@ static void cb(int sock, short which, void *arg) if(s->tickfirst) s->module->tick(s->session); } - litex_sim_eval(vdut); + litex_sim_eval(vsim); litex_sim_dump(); for(s = sesslist; s; s=s->next) { @@ -205,7 +205,7 @@ static void cb(int sock, short which, void *arg) int main(int argc, char *argv[]) { - void *vdut=NULL; + void *vsim=NULL; struct timeval tv; int ret; @@ -225,7 +225,7 @@ int main(int argc, char *argv[]) } litex_sim_init_cmdargs(argc, argv); - if(RC_OK != (ret = litex_sim_initialize_all(&vdut, base))) + if(RC_OK != (ret = litex_sim_initialize_all(&vsim, base))) { goto out; } @@ -237,7 +237,7 @@ int main(int argc, char *argv[]) tv.tv_sec = 0; tv.tv_usec = 0; - ev = event_new(base, -1, EV_PERSIST, cb, vdut); + ev = event_new(base, -1, EV_PERSIST, cb, vsim); event_add(ev, &tv); event_base_dispatch(base); #if VM_COVERAGE diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp index 0f74c340..91474360 100644 --- a/litex/build/sim/core/veril.cpp +++ b/litex/build/sim/core/veril.cpp @@ -3,7 +3,7 @@ #include #include #include -#include "Vdut.h" +#include "Vsim.h" #include "verilated.h" #ifdef TRACE_FST #include "verilated_fst_c.h" @@ -19,10 +19,10 @@ VerilatedVcdC* tfp; long tfp_start; long tfp_end; -extern "C" void litex_sim_eval(void *vdut) +extern "C" void litex_sim_eval(void *vsim) { - Vdut *dut = (Vdut*)vdut; - dut->eval(); + Vsim *sim = (Vsim*)vsim; + sim->eval(); } extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]) @@ -30,20 +30,20 @@ extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]) Verilated::commandArgs(argc, argv); } -extern "C" void litex_sim_init_tracer(void *vdut, long start, long end) +extern "C" void litex_sim_init_tracer(void *vsim, long start, long end) { - Vdut *dut = (Vdut*)vdut; + Vsim *sim = (Vsim*)vsim; tfp_start = start; tfp_end = end; Verilated::traceEverOn(true); #ifdef TRACE_FST tfp = new VerilatedFstC; - dut->trace(tfp, 99); - tfp->open("dut.fst"); + sim->trace(tfp, 99); + tfp->open("sim.fst"); #else tfp = new VerilatedVcdC; - dut->trace(tfp, 99); - tfp->open("dut.vcd"); + sim->trace(tfp, 99); + tfp->open("sim.vcd"); #endif } @@ -69,7 +69,7 @@ extern "C" int litex_sim_got_finish() #if VM_COVERAGE extern "C" void litex_sim_coverage_dump() { - VerilatedCov::write("dut.cov"); + VerilatedCov::write("sim.cov"); } #endif diff --git a/litex/build/sim/core/veril.h b/litex/build/sim/core/veril.h index d0708cdd..4944316e 100644 --- a/litex/build/sim/core/veril.h +++ b/litex/build/sim/core/veril.h @@ -5,16 +5,16 @@ #ifdef __cplusplus extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]); -extern "C" void litex_sim_eval(void *vdut); -extern "C" void litex_sim_init_tracer(void *vdut, long start, long end) +extern "C" void litex_sim_eval(void *vsim); +extern "C" void litex_sim_init_tracer(void *vsim, long start, long end) extern "C" void litex_sim_tracer_dump(); extern "C" int litex_sim_got_finish(); #if VM_COVERAGE extern "C" void litex_sim_coverage_dump(); #endif #else -void litex_sim_eval(void *vdut); -void litex_sim_init_tracer(void *vdut); +void litex_sim_eval(void *vsim); +void litex_sim_init_tracer(void *vsim); void litex_sim_tracer_dump(); int litex_sim_got_finish(); void litex_sim_init_cmdargs(int argc, char *argv[]); diff --git a/litex/build/sim/platform.py b/litex/build/sim/platform.py index 3adb8086..83de4a27 100644 --- a/litex/build/sim/platform.py +++ b/litex/build/sim/platform.py @@ -10,8 +10,8 @@ from litex.build.sim import common, verilator class SimPlatform(GenericPlatform): - def __init__(self, *args, toolchain="verilator", **kwargs): - GenericPlatform.__init__(self, *args, **kwargs) + def __init__(self, *args, name="sim", toolchain="verilator", **kwargs): + GenericPlatform.__init__(self, *args, name=name, **kwargs) self.sim_requested = [] if toolchain == "verilator": self.toolchain = verilator.SimVerilatorToolchain() diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index 2fc25194..d489ab8c 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -45,14 +45,14 @@ void litex_sim_init(void **out); #endif /* __SIM_CORE_H_ */ """ - tools.write_to_file("dut_header.h", content) + tools.write_to_file("sim_header.h", content) def _generate_sim_cpp_struct(name, index, siglist): content = '' for i, (signame, sigbits, sigfname) in enumerate(siglist): - content += ' {}{}[{}].signal = &dut->{};\n'.format(name, index, i, sigfname) + content += ' {}{}[{}].signal = &sim->{};\n'.format(name, index, i, sigfname) idx_int = 0 if not index else int(index) content += ' litex_sim_register_pads({}{}, (char*)"{}", {});\n\n'.format(name, index, name, idx_int) @@ -65,11 +65,11 @@ def _generate_sim_cpp(platform, trace=False, trace_start=0, trace_end=-1): #include #include #include -#include "Vdut.h" +#include "Vsim.h" #include -#include "dut_header.h" +#include "sim_header.h" -extern "C" void litex_sim_init_tracer(void *vdut, long start, long end); +extern "C" void litex_sim_init_tracer(void *vsim, long start, long end); extern "C" void litex_sim_tracer_dump(); extern "C" void litex_sim_dump() @@ -84,21 +84,21 @@ extern "C" void litex_sim_dump() extern "C" void litex_sim_init(void **out) {{ - Vdut *dut; + Vsim *sim; - dut = new Vdut; + sim = new Vsim; - litex_sim_init_tracer(dut, {}, {}); + litex_sim_init_tracer(sim, {}, {}); """.format(trace_start, trace_end) for args in platform.sim_requested: content += _generate_sim_cpp_struct(*args) content += """\ - *out=dut; + *out=sim; } """ - tools.write_to_file("dut_init.cpp", content) + tools.write_to_file("sim_init.cpp", content) def _generate_sim_variables(include_paths): @@ -153,7 +153,7 @@ def _compile_sim(build_name, verbose): def _run_sim(build_name, as_root=False): run_script_contents = "sudo " if as_root else "" - run_script_contents += "obj_dir/Vdut" + run_script_contents += "obj_dir/Vsim" run_script_file = "run_" + build_name + ".sh" tools.write_to_file(run_script_file, run_script_contents, force_unix=True) if sys.platform != "win32": @@ -170,7 +170,7 @@ def _run_sim(build_name, as_root=False): class SimVerilatorToolchain: - def build(self, platform, fragment, build_dir="build", build_name="dut", + def build(self, platform, fragment, build_dir="build", build_name="sim", serial="console", build=True, run=True, threads=1, verbose=True, sim_config=None, coverage=False, opt_level="O0", trace=False, trace_fst=False, trace_start=0, trace_end=-1):