From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 30 Sep 2020 17:14:09 +0000 (+0000)
Subject: commented-out core.size and chip.size which would allow the
X-Git-Tag: partial-core-ls180-gdsii~57
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2eec11b45ed9175955d937e59c4d0ac72062d22d;p=soclayout.git

commented-out core.size and chip.size which would allow the
full core to fit
---

diff --git a/experiments9/coriolis2/ioring.py b/experiments9/coriolis2/ioring.py
index 54b8dcc..027853c 100644
--- a/experiments9/coriolis2/ioring.py
+++ b/experiments9/coriolis2/ioring.py
@@ -186,6 +186,10 @@ chip = { 'pads.ioPadGauge' : 'pxlib',
           'pads.north'      : pn,
           'pads.west'       : pw,
             #[ 'f_3', 'f_2'       , 'p_clk_0', 'f_1'       , 'f_0'     ]
+          # core option (big, time-consuming)
+          #'core.size'       : ( l(26000), l(26000) ),
+          #'chip.size'       : ( l(30000), l(30000) ),
+          # no-core option (test_issuer but no actual core)
           'core.size'       : ( l(13000), l(13000) ),
           'chip.size'       : ( l(17000), l(17000) ),
           'chip.clockTree'  : True,