From: lkcl <lkcl@web>
Date: Sat, 24 Apr 2021 15:09:19 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1020
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2eee873b7730c1e387ae68dc32b71b516be9ef19;p=libreriscv.git

---

diff --git a/docs.mdwn b/docs.mdwn
index 9de4644a6..9d83092d7 100644
--- a/docs.mdwn
+++ b/docs.mdwn
@@ -15,8 +15,7 @@ construction of FSMs and arbitrary length pipelines.
 | [SOC](https://git.libre-soc.org/?p=soc.git;a=tree) | [Libre-SOC](https://docs.libre-soc.org/soc/) | Main OpenPOWER Hybrid CPU-GPU |
 | [FPU](https://git.libre-soc.org/?p=ieee754fpu.git;a=tree) | -- | Equivalent to hardfloat-3 |
 | [nmutil](https://git.libre-soc.org/?p=nmutil.git;a=tree) | -- | Equivalent to Chisel3.util |
-| [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/
-) | Simulator, ISA spec compiler, co-simulation infrastructure |
+| [OpenPOWER ISA](https://git.libre-soc.org/?p=nmutil.git;a=tree) | [OpenPOWER ISA](https://docs.libre-soc.org/openpower-isa/) | Simulator, ISA spec compiler, co-simulation infrastructure |
 
 
 Also see [[SOC Architecture|3d_gpu/architecture]]