From: Ilia Mirkin Date: Sat, 14 May 2016 23:25:15 +0000 (-0400) Subject: nvc0/ir: make sure to align the second arg of TXD to 4, as we do for TEX X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2ef3cdb07e42d985103b5a3e930b2bba676e920b;p=mesa.git nvc0/ir: make sure to align the second arg of TXD to 4, as we do for TEX This was handled in handleTEX(), however the way the logic works, those extra arguments aren't added on by then, so it did nothing. Instead we must duplicate that bit here. GK110 appears to complain about MISALIGNED_GPR, however it's reasonable to believe that GK104 has the same requirements. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95403 Signed-off-by: Ilia Mirkin Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Samuel Pitoiset --- diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 1068c210f89..869b06c2b4c 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -993,6 +993,20 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd) txd->dPdx[c].set(NULL); txd->dPdy[c].set(NULL); } + + // In this case we have fewer than 4 "real" arguments, which means that + // handleTEX didn't apply any padding. However we have to make sure that + // the second "group" of arguments still gets padded up to 4. + if (chipset >= NVISA_GK104_CHIPSET) { + int s = arg + 2 * dim; + if (s >= 4 && s < 7) { + if (txd->srcExists(s)) // move potential predicate out of the way + txd->moveSources(s, 7 - s); + while (s < 7) + txd->setSrc(s++, bld.loadImm(NULL, 0)); + } + } + return true; }