From: Michael Meissner Date: Fri, 26 Aug 1994 20:01:41 +0000 (+0000) Subject: Add -mno-wide-multiply, -mno-move, make addresses more compatible with other parts... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f2a49e848ce398860137ee746fee9d9ad251b97;p=gcc.git Add -mno-wide-multiply, -mno-move, make addresses more compatible with other parts of compiler. From-SVN: r7990 --- diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3e43fb0dea0..04b3a1ee47a 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1,4 +1,4 @@ -;; GCC machine description for Intel 80386. +;; GCC machine description for Intel X86. ;; Copyright (C) 1988, 1994 Free Software Foundation, Inc. ;; Mostly by William Schelter. @@ -157,7 +157,7 @@ if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp,%y0), operands); - return (char *) output_fp_cc0_set (insn); + return output_fp_cc0_set (insn); }") ;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode @@ -190,7 +190,7 @@ if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp,%y0), operands); - return (char *) output_fp_cc0_set (insn); + return output_fp_cc0_set (insn); }") ;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode @@ -223,7 +223,7 @@ if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) output_asm_insn (AS1 (fstp,%y0), operands); - return (char *) output_fp_cc0_set (insn); + return output_fp_cc0_set (insn); }") ;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode @@ -349,7 +349,7 @@ (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -359,7 +359,7 @@ (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -369,7 +369,7 @@ (match_operand:XF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -379,7 +379,7 @@ (match_operand:DF 1 "nonimmediate_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -389,7 +389,7 @@ (match_operand:SF 1 "nonimmediate_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -397,7 +397,7 @@ (match_operand:XF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -407,7 +407,7 @@ (clobber (match_scratch:HI 3 "=a,a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -417,7 +417,7 @@ (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -427,7 +427,7 @@ (match_operand:DF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -437,7 +437,7 @@ (match_operand:SF 1 "nonimmediate_operand" "fm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -447,7 +447,7 @@ (match_operand:DF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -455,7 +455,7 @@ (match_operand:DF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") ;; These two insns will never be generated by combine due to the mode of ;; the COMPARE. @@ -466,7 +466,7 @@ ; (match_operand:SF 1 "register_operand" "f")))) ; (clobber (match_scratch:HI 2 "=a"))] ; "TARGET_80387" -; "* return (char *) output_float_compare (insn, operands);") +; "* return output_float_compare (insn, operands);") ; ;(define_insn "" ; [(set (cc0) @@ -475,7 +475,7 @@ ; (match_operand:DF 1 "register_operand" "f"))) ; (clobber (match_scratch:HI 2 "=a"))] ; "TARGET_80387" -; "* return (char *) output_float_compare (insn, operands);") +; "* return output_float_compare (insn, operands);") (define_insn "cmpsf_cc_1" [(set (cc0) @@ -485,7 +485,7 @@ (clobber (match_scratch:HI 3 "=a,a"))] "TARGET_80387 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -495,7 +495,7 @@ (match_operand:SI 1 "nonimmediate_operand" "rm"))])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -505,7 +505,7 @@ (match_operand:SF 1 "register_operand" "f")])) (clobber (match_scratch:HI 3 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_insn "" [(set (cc0) @@ -513,7 +513,7 @@ (match_operand:SF 1 "register_operand" "f"))) (clobber (match_scratch:HI 2 "=a"))] "TARGET_80387" - "* return (char *) output_float_compare (insn, operands);") + "* return output_float_compare (insn, operands);") (define_expand "cmpxf" [(set (cc0) @@ -740,16 +740,22 @@ (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_operand" "g"))] - "! TARGET_486" + "TARGET_386" "push%L0 %1") ;; On a 486, it is faster to move MEM to a REG and then push, rather than ;; push MEM directly. +(define_insn "" + [(set (match_operand:SI 0 "push_operand" "=<") + (match_operand:SI 1 "nonmemory_operand" "ri"))] + "!TARGET_386 && TARGET_MOVE" + "push%L0 %1") + (define_insn "" [(set (match_operand:SI 0 "push_operand" "=<") (match_operand:SI 1 "general_operand" "ri"))] - "TARGET_486" + "!TARGET_386 && !TARGET_MOVE" "push%L0 %1") ;; General case of fullword move. @@ -767,6 +773,16 @@ if (flag_pic && SYMBOLIC_CONST (operands[1])) emit_pic_move (operands, SImode); + + /* Don't generate memory->memory moves, go through a register */ + else if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM + && (!TARGET_386 || !push_operand (operands[0], SImode))) + { + operands[1] = force_reg (SImode, operands[1]); + } }") ;; On i486, incl reg is faster than movl $1,reg. @@ -774,7 +790,7 @@ (define_insn "" [(set (match_operand:SI 0 "general_operand" "=g,r") (match_operand:SI 1 "general_operand" "ri,m"))] - "" + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" "* { rtx link; @@ -799,15 +815,44 @@ (define_insn "" [(set (match_operand:HI 0 "push_operand" "=<") (match_operand:HI 1 "general_operand" "g"))] - "" + "TARGET_386" + "push%W0 %1") + +(define_insn "" + [(set (match_operand:HI 0 "push_operand" "=<") + (match_operand:HI 1 "nonmemory_operand" "ri"))] + "!TARGET_386 && TARGET_MOVE" + "push%W0 %1") + +(define_insn "" + [(set (match_operand:HI 0 "push_operand" "=<") + (match_operand:HI 1 "general_operand" "ri"))] + "!TARGET_386 && !TARGET_MOVE" "push%W0 %1") ;; On i486, an incl and movl are both faster than incw and movw. -(define_insn "movhi" +(define_expand "movhi" + [(set (match_operand:HI 0 "general_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM + && (!TARGET_386 || !push_operand (operands[0], HImode))) + { + operands[1] = force_reg (HImode, operands[1]); + } +}") + +(define_insn "" [(set (match_operand:HI 0 "general_operand" "=g,r") (match_operand:HI 1 "general_operand" "ri,m"))] - "" + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" "* { rtx link; @@ -837,10 +882,27 @@ return AS2 (mov%W0,%1,%0); }") -(define_insn "movstricthi" +(define_expand "movstricthi" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "")) + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM + && (!TARGET_386 || !push_operand (operands[0], HImode))) + { + operands[1] = force_reg (HImode, operands[1]); + } +}") + +(define_insn "" [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r")) (match_operand:HI 1 "general_operand" "ri,m"))] - "" + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" "* { rtx link; @@ -868,8 +930,24 @@ ;; the amount pushed up to a halfword. (define_insn "" [(set (match_operand:QI 0 "push_operand" "=<") - (match_operand:QI 1 "general_operand" "q"))] + (match_operand:QI 1 "immediate_operand" "n"))] "" + "* return AS1 (push%W0,%1);") + +(define_insn "" + [(set (match_operand:QI 0 "push_operand" "=<") + (match_operand:QI 1 "nonimmediate_operand" "q"))] + "!TARGET_MOVE" + "* +{ + operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); + return AS1 (push%W0,%1); +}") + +(define_insn "" + [(set (match_operand:QI 0 "push_operand" "=<") + (match_operand:QI 1 "register_operand" "q"))] + "TARGET_MOVE" "* { operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); @@ -881,10 +959,27 @@ ;; ??? Do a recognizer for zero_extract that looks just like this, but reads ;; or writes %ah, %bh, %ch, %dh. -(define_insn "movqi" +(define_expand "movqi" + [(set (match_operand:QI 0 "general_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM + && (!TARGET_386 || !push_operand (operands[0], QImode))) + { + operands[1] = force_reg (QImode, operands[1]); + } +}") + +(define_insn "" [(set (match_operand:QI 0 "general_operand" "=q,*r,qm") (match_operand:QI 1 "general_operand" "*g,q,qn"))] - "" + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" "* { rtx link; @@ -919,10 +1014,27 @@ ;; If operands[1] is a constant, then an andl/orl sequence would be ;; faster. -(define_insn "movstrictqi" +(define_expand "movstrictqi" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "")) + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM + && (!TARGET_386 || !push_operand (operands[0], QImode))) + { + operands[1] = force_reg (QImode, operands[1]); + } +}") + +(define_insn "" [(set (strict_low_part (match_operand:QI 0 "general_operand" "+qm,q")) (match_operand:QI 1 "general_operand" "*qn,m"))] - "" + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" "* { rtx link; @@ -1028,14 +1140,14 @@ /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) - return (char *) output_move_const_single (operands); + return output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all SFmode moves not involving the 387 */ - return (char *) singlemove_string (operands); + return singlemove_string (operands); }") ;;should change to handle the memory operands[1] without doing df push.. @@ -1063,7 +1175,7 @@ RET; } else - return (char *) output_move_double (operands); + return output_move_double (operands); }") (define_insn "swapdf" @@ -1129,14 +1241,14 @@ /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) - return (char *) output_move_const_single (operands); + return output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all DFmode moves not involving the 387 */ - return (char *) output_move_double (operands); + return output_move_double (operands); }") (define_insn "" @@ -1161,7 +1273,7 @@ RET; } else - return (char *) output_move_double (operands); + return output_move_double (operands); }") (define_insn "swapxf" @@ -1226,33 +1338,97 @@ /* Handle other kinds of reads to the 387 */ if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) - return (char *) output_move_const_single (operands); + return output_move_const_single (operands); if (STACK_TOP_P (operands[0])) return AS1 (fld%z1,%y1); /* Handle all XFmode moves not involving the 387 */ - return (char *) output_move_double (operands); + return output_move_double (operands); }") (define_insn "" [(set (match_operand:DI 0 "push_operand" "=<") - (match_operand:DI 1 "general_operand" "roiF"))] + (match_operand:DI 1 "general_operand" "roiF")) + (clobber (match_scratch:SI 2 "X")) + (clobber (match_scratch:SI 3 "X"))] + "TARGET_386" + "* return output_move_double (operands);") + +(define_insn "" + [(set (match_operand:DI 0 "push_operand" "=<") + (match_operand:DI 1 "nonmemory_operand" "riF")) + (clobber (match_scratch:SI 2 "X")) + (clobber (match_scratch:SI 3 "X"))] + "!TARGET_386 && TARGET_MOVE" + "* return output_move_double (operands);") + +(define_insn "" + [(set (match_operand:DI 0 "push_operand" "=<") + (match_operand:DI 1 "general_operand" "roiF")) + (clobber (match_scratch:SI 2 "X")) + (clobber (match_scratch:SI 3 "X"))] + "!TARGET_386 && !TARGET_MOVE" + "* return output_move_double (operands);") + +(define_expand "movdi" + [(parallel [(set (match_operand:DI 0 "general_operand" "") + (match_operand:DI 1 "general_operand" "")) + (clobber (match_scratch:SI 2 "")) + (clobber (match_scratch:SI 3 ""))])] "" - "* + " { - return (char *) output_move_double (operands); + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM + && (!TARGET_386 || !push_operand (operands[0], QImode))) + { + operands[1] = force_reg (DImode, operands[1]); + } }") -(define_insn "movdi" - [(set (match_operand:DI 0 "general_operand" "=r,rm") - (match_operand:DI 1 "general_operand" "m,riF"))] - "" - "* -{ - return (char *) output_move_double (operands); +(define_insn "" + [(set (match_operand:DI 0 "general_operand" "=r,rm,o,o") + (match_operand:DI 1 "general_operand" "m,riF,o,o")) + (clobber (match_scratch:SI 2 "X,X,=&r,=&r")) + (clobber (match_scratch:SI 3 "X,X,=&r,X"))] + "" + "* +{ + rtx low[2], high[2], xop[6]; + + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return output_move_double (operands); + + split_di (operands, 2, low, high); + xop[0] = operands[2]; + xop[1] = operands[3]; + xop[2] = high[0]; + xop[3] = high[1]; + xop[4] = low[0]; + xop[5] = low[1]; + if (GET_CODE (operands[3]) == REG) + { /* 2 scratch registers available */ + output_asm_insn (AS2 (mov%L0,%5,%0), xop); + output_asm_insn (AS2 (mov%L0,%3,%1), xop); + output_asm_insn (AS2 (mov%L0,%0,%4), xop); + output_asm_insn (AS2 (mov%L0,%1,%2), xop); + } + else + { /* 1 scratch register */ + output_asm_insn (AS2 (mov%L0,%5,%0), xop); + output_asm_insn (AS2 (mov%L0,%0,%4), xop); + output_asm_insn (AS2 (mov%L0,%3,%0), xop); + output_asm_insn (AS2 (mov%L0,%0,%2), xop); + } + + RET; }") + ;;- conversion instructions ;;- NONE @@ -1778,7 +1954,7 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return (char *) output_fix_trunc (insn, operands);") + "* return output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:DI 0 "general_operand" "=rm") @@ -1788,7 +1964,7 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return (char *) output_fix_trunc (insn, operands);") + "* return output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:DI 0 "general_operand" "=rm") @@ -1798,7 +1974,7 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return (char *) output_fix_trunc (insn, operands);") + "* return output_fix_trunc (insn, operands);") ;; Signed MODE_FLOAT conversion to SImode. @@ -1851,7 +2027,7 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return (char *) output_fix_trunc (insn, operands);") + "* return output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") @@ -1860,7 +2036,7 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return (char *) output_fix_trunc (insn, operands);") + "* return output_fix_trunc (insn, operands);") (define_insn "" [(set (match_operand:SI 0 "general_operand" "=rm") @@ -1869,7 +2045,7 @@ (clobber (match_operand:SI 3 "memory_operand" "m")) (clobber (match_scratch:SI 4 "=&q"))] "TARGET_80387" - "* return (char *) output_fix_trunc (insn, operands);") + "* return output_fix_trunc (insn, operands);") ;; Conversion between fixed point and floating point. ;; The actual pattern that matches these is at the end of this file. @@ -2361,14 +2537,32 @@ [(set (match_operand:DI 0 "register_operand" "=A") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] - "" + "TARGET_WIDE_MULTIPLY" "mul%L0 %2") (define_insn "mulsidi3" [(set (match_operand:DI 0 "register_operand" "=A") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] - "" + "TARGET_WIDE_MULTIPLY" + "imul%L0 %2") + +(define_insn "umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%a")) + (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "=a"))] + "TARGET_WIDE_MULTIPLY" + "mul%L0 %2") + +(define_insn "smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%a")) + (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "=a"))] + "TARGET_WIDE_MULTIPLY" "imul%L0 %2") ;; The patterns that match these are at the end of this file. @@ -5153,7 +5347,7 @@ [(match_operand:DF 1 "nonimmediate_operand" "0,fm") (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") @@ -5161,7 +5355,7 @@ [(float:DF (match_operand:SI 1 "general_operand" "rm")) (match_operand:DF 2 "general_operand" "0")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") @@ -5169,7 +5363,7 @@ [(match_operand:XF 1 "nonimmediate_operand" "0,f") (match_operand:XF 2 "nonimmediate_operand" "f,0")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") @@ -5177,7 +5371,7 @@ [(float:XF (match_operand:SI 1 "general_operand" "rm")) (match_operand:XF 2 "general_operand" "0")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") @@ -5185,7 +5379,7 @@ [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0")) (match_operand:XF 2 "general_operand" "0,f")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f") @@ -5193,7 +5387,7 @@ [(match_operand:XF 1 "general_operand" "0") (float:XF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:XF 0 "register_operand" "=f,f") @@ -5202,7 +5396,7 @@ (float_extend:XF (match_operand:SF 2 "general_operand" "fm,0"))]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -5210,7 +5404,7 @@ [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0")) (match_operand:DF 2 "general_operand" "0,f")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f") @@ -5218,7 +5412,7 @@ [(match_operand:DF 1 "general_operand" "0") (float:DF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:DF 0 "register_operand" "=f,f") @@ -5227,7 +5421,7 @@ (float_extend:DF (match_operand:SF 2 "general_operand" "fm,0"))]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f,f") @@ -5235,7 +5429,7 @@ [(match_operand:SF 1 "nonimmediate_operand" "0,fm") (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5243,7 +5437,7 @@ [(float:SF (match_operand:SI 1 "general_operand" "rm")) (match_operand:SF 2 "general_operand" "0")]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_insn "" [(set (match_operand:SF 0 "register_operand" "=f") @@ -5251,7 +5445,7 @@ [(match_operand:SF 1 "general_operand" "0") (float:SF (match_operand:SI 2 "general_operand" "rm"))]))] "TARGET_80387" - "* return (char *) output_387_binary_op (insn, operands);") + "* return output_387_binary_op (insn, operands);") (define_expand "strlensi" [(parallel [(set (match_dup 4)