From: Siesh1oo <siesh1oo@siesh1oo.no>
Date: Mon, 10 Mar 2014 18:50:02 +0000 (+0100)
Subject:  - frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc/abc.cc: #include <climits>... 
X-Git-Tag: yosys-0.3.0~57^2~1^2~6^2~1^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f2e76ac68dc8da8618ebbf602e2c871f5d4b1b8;p=yosys.git

 - frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc/abc.cc: #include <climits> for PATH_MAX.
---

diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc
index d8568fe94..83035d329 100644
--- a/frontends/vhdl2verilog/vhdl2verilog.cc
+++ b/frontends/vhdl2verilog/vhdl2verilog.cc
@@ -27,6 +27,7 @@
 #include <string.h>
 #include <dirent.h>
 #include <errno.h>
+#include <limits.h>
 
 struct Vhdl2verilogPass : public Pass {
 	Vhdl2verilogPass() : Pass("vhdl2verilog", "importing VHDL designs using vhdl2verilog") { }
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 24a634f65..286b750cc 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -45,6 +45,7 @@
 #include <dirent.h>
 #include <cerrno>
 #include <sstream>
+#include <climits>
 
 #include "blifparse.h"