From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Sat, 20 Dec 2014 15:37:06 +0000 (+0100)
Subject: re PR target/64358 (Wrong code for __int128 operations in powerpc64le)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f40404fb3c073ee55dede450bc7fbbd0da5d8a7;p=gcc.git

re PR target/64358 (Wrong code for __int128 operations in powerpc64le)

	PR target/64358
	* config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the
	input operands if only the second is inverted.
	* config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128):
	Swap BOOL_REGS_OP1 and BOOL_REGS_OP2.  Correct arguments to
	rs6000_split_logical.
	(*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2].

From-SVN: r218989
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bddb9a8b6fb..bee3813269f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2014-12-20  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR target/64358
+	* config/rs6000/rs6000.c (rs6000_split_logical_inner): Swap the
+	input operands if only the second is inverted.
+	* config/rs6000/rs6000.md (*boolc<mode>3_internal1 for BOOL_128):
+	Swap BOOL_REGS_OP1 and BOOL_REGS_OP2.  Correct arguments to
+	rs6000_split_logical.
+	(*boolc<mode>3_internal2 for TI2): Swap operands[1] and operands[2].
+
 2014-12-20  Martin Uecker <uecker@eecs.berkeley.edu>
 
 	* doc/invoke.texi: Document -Wdiscarded-array-qualifiers.
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 73152ce47d1..bbed888b500 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -33167,6 +33167,10 @@ rs6000_split_logical_inner (rtx dest,
   if (complement_op2_p)
     op2 = gen_rtx_NOT (mode, op2);
 
+  /* For canonical RTL, if only one arm is inverted it is the first.  */
+  if (!complement_op1_p && complement_op2_p)
+    std::swap (op1, op2);
+
   bool_rtx = ((code == NOT)
 	      ? gen_rtx_NOT (mode, op1)
 	      : gen_rtx_fmt_ee (code, mode, op1, op2));
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5209c5164e0..7c861c5e955 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7558,8 +7558,8 @@
   [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
 	(match_operator:BOOL_128 3 "boolean_operator"
 	 [(not:BOOL_128
-	   (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
-	  (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
+	   (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))
+	  (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))]
   "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
 {
   if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
@@ -7574,7 +7574,7 @@
    && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
   [(const_int 0)]
 {
-  rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
+  rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
   DONE;
 }
   [(set (attr "type")
@@ -7595,14 +7595,14 @@
   [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
 	(match_operator:TI2 3 "boolean_operator"
 	 [(not:TI2
-	   (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
-	  (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
+	   (match_operand:TI2 2 "int_reg_operand" "r,0,r"))
+	  (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))]
   "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
   "#"
   "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
   [(const_int 0)]
 {
-  rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false);
+  rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true);
   DONE;
 }
   [(set_attr "type" "integer")