From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 18 Mar 2011 00:20:19 +0000 (-0500)
Subject: O3: Fix unaligned stores when cache blocked
X-Git-Tag: stable_2012_02_02~473^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f40b3b8ae4fddcdd167fc86469254f40736c888;p=gem5.git

O3: Fix unaligned stores when cache blocked

Without this change the a store can be issued to the cache multiple times.
If this case occurs when the l1 cache is out of mshrs (and thus blocked)
the processor will never make forward progress because each cycle it will
send a single request using the recently freed mshr and not completing the
multipart store. This will continue forever.
---

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index b5d337935..1a4e686a3 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1103,7 +1103,9 @@ LSQUnit<Impl>::recvRetry()
                 dynamic_cast<LSQSenderState *>(retryPkt->senderState);
 
             // Don't finish the store unless this is the last packet.
-            if (!TheISA::HasUnalignedMemAcc || !state->pktToSend) {
+            if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
+                    state->pendingPacket == retryPkt) {
+                state->pktToSend = false;
                 storePostSend(retryPkt);
             }
             retryPkt = NULL;