From: Luke Kenneth Casson Leighton Date: Mon, 8 Mar 2021 17:21:34 +0000 (+0000) Subject: actually make it possible to disable svp64 on commandline of test_issuer.py X-Git-Tag: convert-csv-opcode-to-binary~83 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f610ea02509eb88e04e666c799f93894b75fff0;p=soc.git actually make it possible to disable svp64 on commandline of test_issuer.py --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index b6032edb..3042da41 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -906,17 +906,21 @@ class PowerDecode2(PowerDecodeSubset): super().__init__(dec, opkls, fn_name, final, state, svp64_en) self.exc = LDSTException("dec2_exc") - self.cr_out_isvec = Signal(1, name="cr_out_isvec") - self.cr_in_isvec = Signal(1, name="cr_in_isvec") - self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec") - self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec") - self.in1_isvec = Signal(1, name="reg_a_isvec") - self.in2_isvec = Signal(1, name="reg_b_isvec") - self.in3_isvec = Signal(1, name="reg_c_isvec") - self.o_isvec = Signal(1, name="reg_o_isvec") - self.o2_isvec = Signal(1, name="reg_o2_isvec") - self.no_in_vec = Signal(1, name="no_in_vec") # no inputs are vectors - self.no_out_vec = Signal(1, name="no_out_vec") # no outputs are vectors + if self.svp64_en: + self.cr_out_isvec = Signal(1, name="cr_out_isvec") + self.cr_in_isvec = Signal(1, name="cr_in_isvec") + self.cr_in_b_isvec = Signal(1, name="cr_in_b_isvec") + self.cr_in_o_isvec = Signal(1, name="cr_in_o_isvec") + self.in1_isvec = Signal(1, name="reg_a_isvec") + self.in2_isvec = Signal(1, name="reg_b_isvec") + self.in3_isvec = Signal(1, name="reg_c_isvec") + self.o_isvec = Signal(1, name="reg_o_isvec") + self.o2_isvec = Signal(1, name="reg_o2_isvec") + self.no_in_vec = Signal(1, name="no_in_vec") # no inputs vector + self.no_out_vec = Signal(1, name="no_out_vec") # no outputs vector + else: + self.no_in_vec = Const(1, 1) + self.no_out_vec = Const(1, 1) def get_col_subset(self, opkls): subset = super().get_col_subset(opkls) @@ -925,14 +929,15 @@ class PowerDecode2(PowerDecodeSubset): subset.add("in2_sel") subset.add("in3_sel") subset.add("out_sel") - subset.add("sv_in1") - subset.add("sv_in2") - subset.add("sv_in3") - subset.add("sv_out") - subset.add("sv_cr_in") - subset.add("sv_cr_out") - subset.add("SV_Etype") - subset.add("SV_Ptype") + if self.svp64_en: + subset.add("sv_in1") + subset.add("sv_in2") + subset.add("sv_in3") + subset.add("sv_out") + subset.add("sv_cr_in") + subset.add("sv_cr_out") + subset.add("SV_Etype") + subset.add("SV_Ptype") subset.add("lk") subset.add("internal_op") subset.add("form") @@ -1106,21 +1111,24 @@ class PowerDecode2(PowerDecodeSubset): comb += to_reg.ok.eq(fromreg.ok) else: - for to_reg, fromreg in ( - (e.read_reg1, dec_a.reg_out), - (e.read_reg2, dec_b.reg_out), - (e.read_reg3, dec_c.reg_out), - (e.write_reg, dec_o.reg_out), - (e.write_ea, dec_o2.reg_out), - (e.read_cr1, self.dec_cr_in), - (e.read_cr2, self.dec_cr_in), - (e.read_cr3, self.dec_cr_in), - (e.write_cr, self.dec_cr_out )): + # connect up to/from read/write GPRs + for to_reg, fromreg in ((e.read_reg1, dec_a.reg_out), + (e.read_reg2, dec_b.reg_out), + (e.read_reg3, dec_c.reg_out), + (e.write_reg, dec_o.reg_out), + (e.write_ea, dec_o2.reg_out)): comb += to_reg.data.eq(fromreg.data) comb += to_reg.ok.eq(fromreg.ok) - comb += self.no_in_vec.eq(1) - comb += self.no_out_vec.eq(1) + # connect up to/from read/write CRs + for to_reg, cr, name in ( + (e.read_cr1, self.dec_cr_in, "cr_bitfield", ), + (e.read_cr2, self.dec_cr_in, "cr_bitfield_b", ), + (e.read_cr3, self.dec_cr_in, "cr_bitfield_o", ), + (e.write_cr, self.dec_cr_out, "cr_bitfield", )): + fromreg = getattr(cr, name) + comb += to_reg.data.eq(fromreg.data) + comb += to_reg.ok.eq(fromreg.ok) # SPRs out comb += e.read_spr1.eq(dec_a.spr_out) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 612fd711..5aa8788e 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -60,6 +60,9 @@ class TestIssuerInternal(Elaboratable): """ def __init__(self, pspec): + # test is SVP64 is to be enabled + self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True) + # JTAG interface. add this right at the start because if it's # added it *modifies* the pspec, by adding enable/disable signals # for parts of the rest of the core @@ -108,8 +111,10 @@ class TestIssuerInternal(Elaboratable): pdecode = create_pdecode() self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE) self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state, - opkls=IssuerDecode2ToOperand) - self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix + opkls=IssuerDecode2ToOperand, + svp64_en=self.svp64_en) + if self.svp64_en: + self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix # Test Instruction memory self.imem = ConfigFetchUnit(pspec).fu @@ -159,7 +164,6 @@ class TestIssuerInternal(Elaboratable): comb = m.d.comb sync = m.d.sync pdecode2 = self.pdecode2 - svp64 = self.svp64 cur_state = self.cur_state dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode @@ -200,25 +204,32 @@ class TestIssuerInternal(Elaboratable): with m.Else(): # not busy: instruction fetched insn = get_insn(self.imem.f_instr_o, cur_state.pc) - # decode the SVP64 prefix, if any - comb += svp64.raw_opcode_in.eq(insn) - comb += svp64.bigendian.eq(self.core_bigendian_i) - # pass the decoded prefix (if any) to PowerDecoder2 - sync += pdecode2.sv_rm.eq(svp64.svp64_rm) - # calculate the address of the following instruction - insn_size = Mux(svp64.is_svp64_mode, 8, 4) - sync += nia.eq(cur_state.pc + insn_size) - with m.If(~svp64.is_svp64_mode): - # with no prefix, store the instruction - # and hand it directly to the next FSM + if self.svp64_en: + svp64 = self.svp64 + # decode the SVP64 prefix, if any + comb += svp64.raw_opcode_in.eq(insn) + comb += svp64.bigendian.eq(self.core_bigendian_i) + # pass the decoded prefix (if any) to PowerDecoder2 + sync += pdecode2.sv_rm.eq(svp64.svp64_rm) + # calculate the address of the following instruction + insn_size = Mux(svp64.is_svp64_mode, 8, 4) + sync += nia.eq(cur_state.pc + insn_size) + with m.If(~svp64.is_svp64_mode): + # with no prefix, store the instruction + # and hand it directly to the next FSM + sync += dec_opcode_i.eq(insn) + m.next = "INSN_READY" + with m.Else(): + # fetch the rest of the instruction from memory + comb += self.imem.a_pc_i.eq(cur_state.pc + 4) + comb += self.imem.a_valid_i.eq(1) + comb += self.imem.f_valid_i.eq(1) + m.next = "INSN_READ2" + else: + # not SVP64 - 32-bit only + sync += nia.eq(cur_state.pc + 4) sync += dec_opcode_i.eq(insn) m.next = "INSN_READY" - with m.Else(): - # fetch the rest of the instruction from memory - comb += self.imem.a_pc_i.eq(cur_state.pc + 4) - comb += self.imem.a_valid_i.eq(1) - comb += self.imem.f_valid_i.eq(1) - m.next = "INSN_READ2" with m.State("INSN_READ2"): with m.If(self.imem.f_busy_o): # zzz... @@ -406,7 +417,6 @@ class TestIssuerInternal(Elaboratable): comb = m.d.comb sync = m.d.sync pdecode2 = self.pdecode2 - svp64 = self.svp64 # temporaries core_busy_o = core.busy_o # core is busy @@ -481,7 +491,8 @@ class TestIssuerInternal(Elaboratable): # instruction decoder pdecode = create_pdecode() m.submodules.dec2 = pdecode2 = self.pdecode2 - m.submodules.svp64 = svp64 = self.svp64 + if self.svp64_en: + m.submodules.svp64 = svp64 = self.svp64 # convenience dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer diff --git a/src/soc/simple/test/test_issuer.py b/src/soc/simple/test/test_issuer.py index 47d112a7..3170cfbb 100644 --- a/src/soc/simple/test/test_issuer.py +++ b/src/soc/simple/test/test_issuer.py @@ -32,6 +32,8 @@ if __name__ == "__main__": svp64 = False sys.argv.pop() + print ("SVP64 test mode enabled", svp64) + unittest.main(exit=False) suite = unittest.TestSuite() # suite.addTest(TestRunner(HelloTestCases.test_data, svp64=svp64))