From: Terry Guo Date: Tue, 30 Sep 2014 10:02:39 +0000 (+0000) Subject: arm-cores.def (cortex-m7): New core name. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f6403f1337686599ddce4c01798274081fe2c35;p=gcc.git arm-cores.def (cortex-m7): New core name. 2014-09-30 Terry Guo * config/arm/arm-cores.def (cortex-m7): New core name. * config/arm/arm-fpus.def (fpv5-sp-d16): New fpu name. (fpv5-d16): Ditto. * config/arm/arm-tables.opt: Regenerated. * config/arm/arm-tune.md: Regenerated. * config/arm/arm.h (TARGET_VFP5): New macro. * config/arm/bpabi.h (BE8_LINK_SPEC): Include cortex-m7. * config/arm/vfp.md (2, smax3, smin3): Enabled for FPU FPv5. * doc/invoke.texi: Document new cpu and fpu names. From-SVN: r215711 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9e78a93f569..766e935638b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2014-09-30 Terry Guo + + * config/arm/arm-cores.def (cortex-m7): New core name. + * config/arm/arm-fpus.def (fpv5-sp-d16): New fpu name. + (fpv5-d16): Ditto. + * config/arm/arm-tables.opt: Regenerated. + * config/arm/arm-tune.md: Regenerated. + * config/arm/arm.h (TARGET_VFP5): New macro. + * config/arm/bpabi.h (BE8_LINK_SPEC): Include cortex-m7. + * config/arm/vfp.md (2, + smax3, smin3): Enabled for FPU FPv5. + * doc/invoke.texi: Document new cpu and fpu names. + 2014-09-30 Jiong Wang * shrink-wrap.c (move_insn_for_shrink_wrap): Check "can_throw_internal" diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index a830a83baeb..56ec7fd8fe7 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -149,6 +149,7 @@ ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, FL_LDSCHED, cortex) ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, FL_LDSCHED | FL_ARM_DIV, cortex) +ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, FL_LDSCHED, v7m) ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, FL_LDSCHED, v7m) ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, FL_LDSCHED, v7m) ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, FL_LDSCHED, 9e) diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index 85d9693c1fe..edd0c352474 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -37,6 +37,8 @@ ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true, false) ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false) ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false) ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, false) +ARM_FPU("fpv5-sp-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, false, true, false) +ARM_FPU("fpv5-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_D16, false, true, false) ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false) ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false) ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, false) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index bc046a0de8e..04191bceefb 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -273,6 +273,9 @@ Enum(processor_type) String(cortex-r5) Value(cortexr5) EnumValue Enum(processor_type) String(cortex-r7) Value(cortexr7) +EnumValue +Enum(processor_type) String(cortex-m7) Value(cortexm7) + EnumValue Enum(processor_type) String(cortex-m4) Value(cortexm4) @@ -423,17 +426,23 @@ EnumValue Enum(arm_fpu) String(fpv4-sp-d16) Value(11) EnumValue -Enum(arm_fpu) String(neon-vfpv4) Value(12) +Enum(arm_fpu) String(fpv5-sp-d16) Value(12) + +EnumValue +Enum(arm_fpu) String(fpv5-d16) Value(13) + +EnumValue +Enum(arm_fpu) String(neon-vfpv4) Value(14) EnumValue -Enum(arm_fpu) String(fp-armv8) Value(13) +Enum(arm_fpu) String(fp-armv8) Value(15) EnumValue -Enum(arm_fpu) String(neon-fp-armv8) Value(14) +Enum(arm_fpu) String(neon-fp-armv8) Value(16) EnumValue -Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(15) +Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(17) EnumValue -Enum(arm_fpu) String(vfp3) Value(16) +Enum(arm_fpu) String(vfp3) Value(18) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 954cab8efb1..4217fbe8b2c 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -28,7 +28,8 @@ genericv7a,cortexa5,cortexa7, cortexa8,cortexa9,cortexa12, cortexa15,cortexr4,cortexr4f, - cortexr5,cortexr7,cortexm4, - cortexm3,marvell_pj4,cortexa15cortexa7, - cortexa53,cortexa57,cortexa57cortexa53" + cortexr5,cortexr7,cortexm7, + cortexm4,cortexm3,marvell_pj4, + cortexa15cortexa7,cortexa53,cortexa57, + cortexa57cortexa53" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ff4ddace2b5..3623c70441e 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -296,6 +296,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void); /* FPU supports VFPv3 instructions. */ #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) +/* FPU supports FPv5 instructions. */ +#define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5) + /* FPU only supports VFP single-precision instructions. */ #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index 7a576ac466c..9a471c251a8 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -73,7 +73,7 @@ |mcpu=generic-armv7-a \ |march=armv7ve \ |march=armv7-m|mcpu=cortex-m3 \ - |march=armv7e-m|mcpu=cortex-m4 \ + |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \ |march=armv6-m|mcpu=cortex-m0 \ |march=armv8-a \ :%{!r:--be8}}}" @@ -91,7 +91,7 @@ |mcpu=generic-armv7-a \ |march=armv7ve \ |march=armv7-m|mcpu=cortex-m3 \ - |march=armv7e-m|mcpu=cortex-m4 \ + |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \ |march=armv6-m|mcpu=cortex-m0 \ |march=armv8-a \ :%{!r:--be8}}}" diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index a2034498518..6522c9082fa 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1298,7 +1298,7 @@ (unspec:SDF [(match_operand:SDF 1 "register_operand" "")] VRINT))] - "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " + "TARGET_HARD_FLOAT && TARGET_VFP5 " "vrint%?.\\t%0, %1" [(set_attr "predicable" "") (set_attr "predicable_short_it" "no") @@ -1329,7 +1329,7 @@ [(set (match_operand:SDF 0 "register_operand" "=") (smax:SDF (match_operand:SDF 1 "register_operand" "") (match_operand:SDF 2 "register_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " + "TARGET_HARD_FLOAT && TARGET_VFP5 " "vmaxnm.\\t%0, %1, %2" [(set_attr "type" "f_minmax") (set_attr "conds" "unconditional")] @@ -1339,7 +1339,7 @@ [(set (match_operand:SDF 0 "register_operand" "=") (smin:SDF (match_operand:SDF 1 "register_operand" "") (match_operand:SDF 2 "register_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 " + "TARGET_HARD_FLOAT && TARGET_VFP5 " "vminnm.\\t%0, %1, %2" [(set_attr "type" "f_minmax") (set_attr "conds" "unconditional")] diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f6c3b420da1..5fe7e15b4e9 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12632,7 +12632,8 @@ Permissible names are: @samp{arm2}, @samp{arm250}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-r4}, -@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m4}, +@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7}, +@samp{cortex-m4}, @samp{cortex-m3}, @samp{cortex-m1}, @samp{cortex-m0}, @@ -12686,6 +12687,7 @@ available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3}, @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, +@samp{fpv5-d16}, @samp{fpv5-sp-d16}, @samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}. If @option{-msoft-float} is specified this specifies the format of