From: Ron Dreslinski Date: Tue, 31 Jan 2006 19:39:41 +0000 (-0500) Subject: Fixed some void functions with returns, first stab at cpu ports. X-Git-Tag: m5_2.0_beta1~242 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f644efafaa6df54f4e9b8f2710aa6f3647b6940;p=gem5.git Fixed some void functions with returns, first stab at cpu ports. cpu/simple/cpu.hh: Adding port definitions to simple cpu, still needs work. mem/bus.hh: no return for void functions --HG-- extra : convert_revision : 42e5bc16af187d3a46eb25a15b600a8a11b88cc5 --- diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh index 0f7251237..30fea0f86 100644 --- a/cpu/simple/cpu.hh +++ b/cpu/simple/cpu.hh @@ -63,6 +63,40 @@ namespace Trace { class SimpleCPU : public BaseCPU { + class CpuPort : public Port + { + + SimpleCPU *cpu; + + public: + + CpuPort(SimpleCPU *_cpu) + : cpu(_cpu) + { } + + protected: + + virtual bool recvTiming(Packet &pkt) + { return cpu->recvTiming(pkt); } + + virtual Tick recvAtomic(Packet &pkt) + { return cpu->recvAtomic(pkt); } + + virtual void recvFunctional(Packet &pkt) + { cpu->recvFunctional(pkt); } + + virtual void recvStatusChange(Status status) + { cpu->recvStatusChange(status); } + + }; + + CpuPort icache_port; + CpuPort dcache_port; + + bool recvTiming(Packet &pkt); + Tick recvAtomic(Packet &pkt); + void recvFunctional(Packet &pkt); + public: // main simulation loop (one cycle) void tick(); diff --git a/mem/bus.hh b/mem/bus.hh index 0fd450c4f..e1b29bac6 100644 --- a/mem/bus.hh +++ b/mem/bus.hh @@ -92,7 +92,7 @@ class Bus : public MemObject /** When reciving a Functional requestfrom the peer port (at id), pass it to the bus. */ virtual void recvFunctional(Packet &pkt) - { return bus->recvFunctional(pkt, id); } + { bus->recvFunctional(pkt, id); } /** When reciving a status changefrom the peer port (at id), pass it to the bus. */