From: Michael Nolan <mtnolan2640@gmail.com>
Date: Tue, 2 Jun 2020 20:23:28 +0000 (-0400)
Subject: Select spr1 for bcctr - use fast_spr decoding from decoder
X-Git-Tag: div_pipeline~637^2~36
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f6a9506dc6e9ac8604580cfe62f9725922d67b2;p=soc.git

Select spr1 for bcctr - use fast_spr decoding from decoder
---

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index f145a632..0e9e7f57 100644
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -134,7 +134,11 @@ class BranchMainStage(PipeModBase):
                 comb += ctr_o.ok.eq(ctr_write)
             #### branch conditional reg ####
             with m.Case(InternalOp.OP_BCREG):
-                comb += br_imm_addr.eq(Cat(Const(0, 2), spr2[2:]))
+                xo = self.fields.FormXL.XO[0:-1]
+                with m.If(xo[9] & ~xo[5]):
+                    comb += br_imm_addr.eq(Cat(Const(0, 2), spr1[2:]))
+                with m.Else():
+                    comb += br_imm_addr.eq(Cat(Const(0, 2), spr2[2:]))
                 comb += br_taken.eq(bc_taken)
                 comb += ctr_o.ok.eq(ctr_write)
 
diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index c14ed974..b2b05f05 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -224,33 +224,20 @@ class TestRunner(FHDLTestCase):
         print(f"cr0: {sim.crl[0].get_range()}")
 
         # TODO: this needs to now be read_fast1.data and read_fast2.data
-        if False:
-            fast1_en = yield dec2.e.read_fast1.ok
-            if fast1_en:
-                fast1_sel = yield dec2.e.read_fast1.data
-                spr1_sel = fast_reg_to_spr(fast1_sel)
-                spr1_data = sim.spr[spr1_sel].value
-                yield branch.p.data_i.spr1.eq(spr1_data)
-
-            fast2_en = yield dec2.e.read_fast2.ok
-            if fast2_en:
-                fast2_sel = yield dec2.e.read_fast2.data
-                spr2_sel = fast_reg_to_spr(fast2_sel)
-                spr2_data = sim.spr[spr2_sel].value
-                yield branch.p.data_i.spr2.eq(spr2_data)
-
-        # TODO: drop this once it's in PowerDecode2
-        # (actually, DecodeA and DecodeB)
-        insn_type = yield dec2.e.insn_type
-        if insn_type == InternalOp.OP_BCREG.value:
-            xo9 = yield dec2.dec.FormXL.XO[9]
-            xo5 = yield dec2.dec.FormXL.XO[5]
-            if xo9 == 0:
-                yield branch.p.data_i.spr2.eq(sim.spr['LR'].value)
-            elif xo5 == 1:
-                yield branch.p.data_i.spr2.eq(sim.spr['TAR'].value)
-            else:
-                yield branch.p.data_i.spr2.eq(sim.spr['CTR'].value)
+        fast1_en = yield dec2.e.read_fast1.ok
+        if fast1_en:
+            fast1_sel = yield dec2.e.read_fast1.data
+            spr1_sel = fast_reg_to_spr(fast1_sel)
+            spr1_data = sim.spr[spr1_sel].value
+            yield branch.p.data_i.spr1.eq(spr1_data)
+
+        fast2_en = yield dec2.e.read_fast2.ok
+        if fast2_en:
+            fast2_sel = yield dec2.e.read_fast2.data
+            spr2_sel = fast_reg_to_spr(fast2_sel)
+            spr2_data = sim.spr[spr2_sel].value
+            yield branch.p.data_i.spr2.eq(spr2_data)
+
 
         cr_en = yield dec2.e.read_cr1.ok
         if cr_en: