From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Tue, 14 Apr 2020 16:59:49 +0000 (+0200)
Subject: opt_expr: Fix X and CO outputs for $alu identity-mapping rules.
X-Git-Tag: working-ls180~637
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2f8541a92eb6a733c90170709c4c597452036ab6;p=yosys.git

opt_expr: Fix X and CO outputs for $alu identity-mapping rules.
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 3229dd1b2..2b35ace5e 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1135,9 +1135,24 @@ skip_fine_alu:
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
 
 				if (cell->type == ID($alu)) {
+					bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
+					bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
+					bool is_signed = a_signed && b_signed;
+					RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
 					int y_width = GetSize(cell->getPort(ID::Y));
-					module->connect(cell->getPort(ID::X), RTLIL::Const(State::S0, y_width));
-					module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S0, y_width));
+					if (sig_ci == State::S1) {
+						/* sub, b is 0 */
+						RTLIL::SigSpec a = cell->getPort(ID::A);
+						a.extend_u0(y_width, is_signed);
+						module->connect(cell->getPort(ID::X), module->Not(NEW_ID, a));
+						module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S1, y_width));
+					} else {
+						/* add */
+						RTLIL::SigSpec ab = cell->getPort(identity_wrt_a ? ID::A : ID::B);
+						ab.extend_u0(y_width, is_signed);
+						module->connect(cell->getPort(ID::X), ab);
+						module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S0, y_width));
+					}
 					cell->unsetPort(ID::BI);
 					cell->unsetPort(ID::CI);
 					cell->unsetPort(ID::X);
diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys
index e288bcea6..9121c0096 100644
--- a/tests/opt/opt_expr_alu.ys
+++ b/tests/opt/opt_expr_alu.ys
@@ -8,7 +8,7 @@ alumacc
 equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-none t:$pos t:* %D
 
 
 design -reset
@@ -20,7 +20,7 @@ EOT
 
 alumacc
 select -assert-count 1 t:$alu
-select -assert-count none t:$alu t:* %D
+select -assert-none t:$alu t:* %D
 
 
 design -reset
@@ -33,7 +33,7 @@ EOT
 equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-none t:$pos t:* %D
 
 
 design -reset
@@ -46,7 +46,7 @@ EOT
 equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-none t:$pos t:* %D
 
 
 design -reset
@@ -60,7 +60,8 @@ alumacc
 equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$pos
-select -assert-count none t:$pos t:* %D
+select -assert-count 1 t:$not
+select -assert-none t:$pos t:$not %% t:* %D
 
 
 design -reset
@@ -76,7 +77,7 @@ design -load postopt
 select -assert-count 1 t:$alu
 select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
 select -assert-count 1 t:$not
-select -assert-count none t:$alu t:$not t:* %D %D
+select -assert-none t:$alu t:$not t:* %D %D
 
 
 design -reset
@@ -93,7 +94,7 @@ dump
 select -assert-count 2 t:$alu
 select -assert-count 1 t:$alu r:Y_WIDTH=2 %i
 select -assert-count 1 t:$alu r:Y_WIDTH=3 %i
-select -assert-count none t:$alu t:* %D
+select -assert-none t:$alu t:* %D
 
 
 design -reset
@@ -108,4 +109,61 @@ equiv_opt -assert opt -fine
 design -load postopt
 select -assert-count 2 t:$alu
 select -assert-count 2 t:$alu r:Y_WIDTH=3 %i
-select -assert-count none t:$alu t:* %D
+select -assert-none t:$alu t:* %D
+
+
+design -reset
+read_verilog -icells <<EOT
+module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
+$alu #(
+	.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+	.A_SIGNED(0), .B_SIGNED(0),
+) alu (
+	.A(a), .B(4'h0),
+	.BI(1'b0), .CI(1'b0),
+	.Y(y), .X(x), .CO(co),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt
+design -load postopt
+select -assert-none t:$alu
+
+
+design -reset
+read_verilog -icells <<EOT
+module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
+$alu #(
+	.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+	.A_SIGNED(0), .B_SIGNED(0),
+) alu (
+	.A(a), .B(4'h0),
+	.BI(1'b1), .CI(1'b1),
+	.Y(y), .X(x), .CO(co),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt
+design -load postopt
+select -assert-none t:$alu
+
+
+design -reset
+read_verilog -icells <<EOT
+module test(input [3:0] a, output [3:0] y, output [3:0] x, output [3:0] co);
+$alu #(
+	.A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(4),
+	.A_SIGNED(0), .B_SIGNED(0),
+) alu (
+	.A(4'h0), .B(a),
+	.BI(1'b0), .CI(1'b0),
+	.Y(y), .X(x), .CO(co),
+);
+endmodule
+EOT
+
+equiv_opt -assert opt
+design -load postopt
+select -assert-none t:$alu